Lukas Plevac
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e662c52e75
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Static write FA to PGAdder
BUILD / test (push) Successful in 1m51s
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2025-01-19 19:10:26 +01:00 |
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Lukas Plevac
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6c8c791fb5
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Code generation fix
BUILD / test (push) Successful in 1m56s
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2025-01-19 18:34:41 +01:00 |
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db25df54cd
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unexpected keyword argument 'parent_component'
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2025-01-15 19:33:13 +01:00 |
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cf4a6ccc52
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Incorect FA instance create
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2025-01-15 19:31:12 +01:00 |
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aefc20693a
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Full adder missing import
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2025-01-15 19:28:29 +01:00 |
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395750eac5
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Imprt missing full adder
BUILD / test (push) Failing after 17s
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2025-01-15 19:23:47 +01:00 |
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d0501238f8
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GCP PGA ADDER
BUILD / test (push) Failing after 25s
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2025-01-06 13:03:21 +01:00 |
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Lukas Plevac
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c9c99fbb11
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Optimalize MUX
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2024-11-16 20:54:41 +01:00 |
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c476479827
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Fix mux with wrong gate ordering
BUILD / test (push) Blocked by required conditions
CodeQL / Analyze (python) (push) Failing after 39s
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2024-11-14 15:15:17 +01:00 |
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Lukas Plevac
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4eb65e10da
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All working muls and adders
BUILD / Python ${{ matrix.python-version }} test (3.11) (push) Has been cancelled
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BUILD / build (push) Failing after 5m29s
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CodeQL / Analyze (python) (push) Failing after 45s
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2024-10-17 19:11:02 +02:00 |
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Lukas Plevac
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09a12f3df7
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Fully working xorGateComponent
CodeQL / Analyze (python) (push) Has been cancelled
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2024-10-10 13:33:09 +02:00 |
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Lukas Plevac
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c61244c966
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Fixed RCA by test
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2024-10-08 14:28:38 +02:00 |
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Lukas Plevac
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6132c3c449
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Optimalized MAJ implementation for adders
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2024-10-08 13:39:48 +02:00 |
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Lukas Plevac
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ad9f62e3de
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Added support for MIG excluded xor and xnor gate
CodeQL / Analyze (python) (push) Waiting to run
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BUILD / Python ${{ matrix.python-version }} test (3.10) (push) Blocked by required conditions
BUILD / Python ${{ matrix.python-version }} test (3.11) (push) Blocked by required conditions
BUILD / Python ${{ matrix.python-version }} test (3.7) (push) Blocked by required conditions
BUILD / Python ${{ matrix.python-version }} test (3.8) (push) Blocked by required conditions
BUILD / Python ${{ matrix.python-version }} test (3.9) (push) Blocked by required conditions
BUILD / documentation (push) Blocked by required conditions
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2024-10-07 15:19:55 +02:00 |
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Vojta
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813f111df7
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Merge branch 'devel' of github.com:ehw-fit/ariths-gen into devel
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2024-10-03 08:19:27 +02:00 |
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Vojta
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c1e8680e83
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CGP with more than 26 inputs naming
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2024-10-03 08:18:49 +02:00 |
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honzastor
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b87f8350fc
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Added ripple borrow subtractor circuit and updated automated testing.
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2024-10-01 18:42:11 +02:00 |
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Vojta Mrazek
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bc95444995
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reconnected wire was not identified as a bus
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2024-07-22 15:10:21 +02:00 |
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Vojta Mrazek
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04cd3e44d3
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bug in cgp indexes with constant wires, they were encouted
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2024-07-22 15:09:50 +02:00 |
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Vojta Mrazek
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f34471bfe3
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signed version of python code
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2024-07-18 13:16:15 +02:00 |
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Vojta Mrazek
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4cd1189d4a
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CGP circuit accepts BUS inputs
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2024-07-18 13:15:56 +02:00 |
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Vojta Mrazek
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bc0104de12
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ripple cary subtractor
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2024-07-09 09:22:11 +02:00 |
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Vojta Mrazek
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e41b4a2f2c
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Merge branch 'devel' of github.com:ehw-fit/ariths-gen into devel
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2024-07-08 11:31:30 +02:00 |
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Vojta Mrazek
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c480eeacf9
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popcount parent component
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2024-07-08 11:29:25 +02:00 |
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honzastor
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ce36ebf77b
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Fixed hierarchical BLIF generation for popcount_compare.
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2024-04-17 18:47:41 +02:00 |
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honzastor
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6003886eb7
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Fixed hierarchical Verilog generation of popcount compare. BLIF probably needs a similar treatment, TBD later
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2024-04-14 16:29:10 +02:00 |
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honzastor
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97e79b93da
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Big code cleanup and some fixes. Hierarchical generation for popcount seems problematic. It seems bus connections are the issue.
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2024-04-13 17:04:03 +02:00 |
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honzastor
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739d5fafce
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Added documentation to Recursive multiplier and hopefully fixed some issues with popcount output generation.
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2024-04-08 21:37:34 +02:00 |
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Vojta Mrazek
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4e331f0525
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popcount with variable sizes
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2024-04-08 13:48:25 +02:00 |
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Vojta Mrazek
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128b1309a1
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popcount fixes
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2024-04-05 09:24:03 +02:00 |
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Vojta Mrazek
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1219d7bec5
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Merge branch 'popcount' into devel
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2024-04-05 09:19:04 +02:00 |
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Vojta Mrazek
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2cf7b921ea
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Popcount implementation
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2024-04-05 08:46:02 +02:00 |
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honzastor
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da733cf44e
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Added instantiation of wires and buses from inputs. Hopefully fixed now.
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2024-03-28 00:06:53 +01:00 |
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honzastor
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21a6437eb8
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Additional type hint fix.
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2024-03-27 23:19:40 +01:00 |
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honzastor
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73101eb055
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Type hint bugfix for pytest.
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2024-03-27 23:10:06 +01:00 |
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honzastor
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d013a40145
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Added unsigned recursive multiplier and made some bugfixes.
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2024-03-27 23:00:13 +01:00 |
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Vojta Mrazek
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2e1694ccd5
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popcount and compare
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2024-03-22 14:19:23 +01:00 |
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honzastor
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7e1112cf81
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Added individual input bus attributes to CGP Circuit objects to allow for the generation of output CGP representation.
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2024-03-06 00:42:12 +01:00 |
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Vojta Mrazek
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f853a46703
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CGP circuit checks
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2023-04-13 12:09:07 +02:00 |
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Vojta Mrazek
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a44b0638a1
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Implementation of QuAd approximate adder
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2023-03-28 13:55:58 +02:00 |
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Vojta Mrazek
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a4741db191
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connection checks (asserts)
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2023-03-28 11:16:55 +02:00 |
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Vojta Mrazek
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44e0a920d1
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MUX support of constant values
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2023-03-24 12:11:42 +01:00 |
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Vojta Mrazek
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49bbc86a0f
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accepts a wire as a bus
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2023-03-23 13:39:32 +01:00 |
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honzastor
|
7cf34d04f3
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Bugfix in conditional statement.
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2023-03-22 18:14:55 +01:00 |
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honzastor
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b88c502343
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Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated).
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2023-03-22 17:57:51 +01:00 |
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honzastor
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d52e67bb25
|
Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.
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2023-02-24 11:13:46 +01:00 |
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Vojta Mrazek
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283f9c79f5
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Merge branch 'main' into devel
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2023-02-22 12:12:20 +01:00 |
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Vojta Mrazek
|
6dd69c5aaa
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Merge branch 'devel' of github.com:ehw-fit/ariths-gen into devel
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2023-02-22 09:52:34 +01:00 |
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Vojta Mrazek
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43b3d65463
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workflow modification, bus indexing
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2023-02-22 09:52:06 +01:00 |
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Vojta Mrazek
|
71a1d45045
|
string description (#15)
|
2023-02-22 09:45:14 +01:00 |
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