honzastor b88c502343 Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated).

2023-03-22 17:57:51 +01:00

..

core

Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated).

2023-03-22 17:57:51 +01:00

multi_bit_circuits

Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.

2023-02-24 11:13:46 +01:00

one_bit_circuits

Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated).

2023-03-22 17:57:51 +01:00

wire_components

Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.

2023-02-24 11:13:46 +01:00

__init__.py

Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.

2023-02-24 11:13:46 +01:00

pdk.py

Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated).

2023-03-22 17:57:51 +01:00