dissertation_thesis/ariths-gen-mig
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unexpected keyword argument 'parent_component'
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Lukáš Plevač 2025-01-15 19:33:13 +01:00
parent cf4a6ccc52
commit db25df54cd
1 changed files with 1 additions and 1 deletions
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ariths_gen/one_bit_circuits/one_bit_components/two_input_one_bit_components.py
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@ -209,7 +209,7 @@ class partialAdder(TwoInputOneBitCircuit):
generate_and = AndGate(a, b, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), outid=1, parent_component=self)
self.add_component(generate_and)
fa = FullAdder(a, b, cin, prefix=self.prefix+"_fa" +str(self.get_instance_num(cls=FullAdder)), parent_component=self)
fa = FullAdder(a, b, cin, prefix=self.prefix+"_fa" +str(self.get_instance_num(cls=FullAdder)))
self.add_component(fa)
self.out.connect(0, propagate_or.out)