dissertation_thesis/ariths-gen-mig
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

All working muls and adders
Some checks failed
BUILD / Python ${{ matrix.python-version }} test (3.11) (push) Has been cancelled
Details
BUILD / Python ${{ matrix.python-version }} test (3.7) (push) Has been cancelled
Details
BUILD / Python ${{ matrix.python-version }} test (3.8) (push) Has been cancelled
Details
BUILD / Python ${{ matrix.python-version }} test (3.9) (push) Has been cancelled
Details
BUILD / build (push) Failing after 5m29s
Details
BUILD / test (push) Has been skipped
Details
BUILD / Python ${{ matrix.python-version }} test (3.10) (push) Has been skipped
Details
BUILD / documentation (push) Has been skipped
Details
CodeQL / Analyze (python) (push) Failing after 45s
Details

Browse Source
This commit is contained in:
Lukas Plevac 2024-10-17 19:11:02 +02:00
parent 09a12f3df7
commit 4eb65e10da
3 changed files with 58 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
ariths_gen/one_bit_circuits/one_bit_components/__init__.py
View File

@ -1,6 +1,8 @@
from .two_input_one_bit_components import (
HalfAdder,
HalfSubtractor,
XorGateComponent,
XnorGateComponent,
PGLogicBlock
)
@ -8,8 +10,6 @@ from .three_input_one_bit_components import (
FullAdder,
FullAdderP,
FullAdderPG,
XorGateComponent,
XnorGateComponent,
PGSumLogic,
TwoOneMultiplexer,
FullSubtractor,

52
ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py
View File

@ -2,7 +2,6 @@ from ariths_gen.one_bit_circuits import Maji
from ariths_gen.wire_components.wires import ConstantWireValue0
from ariths_gen.core.one_bit_circuits import ThreeInputOneBitCircuit
from ariths_gen.one_bit_circuits.logic_gates import AndGate, NandGate, OrGate, NorGate, NotGate
from .two_input_one_bit_components import XorGateComponent, XnorGateComponent
from ariths_gen.wire_components import Wire, Bus
@ -130,7 +129,17 @@ class FullAdderP(FullAdder, ThreeInputOneBitCircuit):
super().__init__(a, b, c, prefix=prefix, name=name)
# 3 wires for component's bus output (sum, cout, propagate)
self.out.bus_extend(3)
self.out.connect(2, self.get_previous_component(5).out)
propagate_or = OrGate (a, b, prefix=self.prefix+"_or" +str(self.get_instance_num(cls=OrGate)), outid=0, parent_component=self)
self.add_component(propagate_or)
generate_and = AndGate(a, b, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), outid=1, parent_component=self)
self.add_component(generate_and)
propagate_xor = Maji(propagate_or.out, generate_and.out, ConstantWireValue0(), [False, True, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=0, parent_component=self)
self.add_component(propagate_xor)
self.out.connect(2, propagate_xor.out)
def get_propagate_wire(self):
"""Get output wire carrying propagate value.
@ -212,18 +221,28 @@ class PGSumLogic(ThreeInputOneBitCircuit):
self.out = Bus(self.prefix+"_out", 3)
# PG logic
propagate_xor = XorGateComponent(a, b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), outid=0, parent_component=self)
self.add_component(propagate_xor)
self.out.connect(0, propagate_xor.out.get_wire(0))
propagate_or = OrGate (a, b, prefix=self.prefix+"_or" +str(self.get_instance_num(cls=OrGate)), outid=0, parent_component=self)
self.add_component(propagate_or)
generate_and = AndGate(a, b, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), outid=1, parent_component=self)
self.add_component(generate_and)
self.out.connect(1, generate_and.out)
propagate_xor = Maji(propagate_or.out, generate_and.out, ConstantWireValue0(), [False, True, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=0, parent_component=self)
self.add_component(propagate_xor)
self.out.connect(0, propagate_xor.out)
# Sum output
sum_xor = XorGateComponent(propagate_xor.out.get_wire(0), c, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), outid=2, parent_component=self)
self.add_component(sum_xor)
self.out.connect(2, sum_xor.out.get_wire(0))
obj_or2 = OrGate (propagate_xor.out, c, prefix=self.prefix+"_or" +str(self.get_instance_num(cls=OrGate)), parent_component=self)
self.add_component(obj_or2)
obj_and2 = AndGate(propagate_xor.out, c, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), parent_component=self)
self.add_component(obj_and2)
# final sum
obj_maji = Maji(obj_or2.out, obj_and2.out, ConstantWireValue0(), [False, True, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=2, parent_component=self)
self.add_component(obj_maji)
self.out.connect(2, obj_maji.out)
def get_propagate_wire(self):
"""Get output wire carrying propagate signal value.
@ -290,11 +309,20 @@ class TwoOneMultiplexer(ThreeInputOneBitCircuit):
and_obj = AndGate(a=self.a, b=self.get_previous_component().out, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), parent_component=self)
self.add_component(and_obj)
xor_obj = XorGateComponent(a=self.get_previous_component(3).out, b=self.get_previous_component().out, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self)
self.add_component(xor_obj)
# final xor
obj_or2 = OrGate (a=self.get_previous_component(3).out, b=self.get_previous_component().out, prefix=self.prefix+"_or" +str(self.get_instance_num(cls=OrGate)), parent_component=self)
self.add_component(obj_or2)
obj_and2 = AndGate(a=self.get_previous_component(3).out, b=self.get_previous_component().out, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), parent_component=self)
self.add_component(obj_and2)
# final sum
obj_maji = Maji(obj_or2.out, obj_and2.out, ConstantWireValue0(), [False, True, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), parent_component=self)
self.add_component(obj_maji)
# Connection of MUX output wire
self.out.connect(0, xor_obj.out.get_wire(0))
self.out.connect(0, obj_maji.out)
def get_mux_out_wire(self):
"""Get multiplexer output wire.

22
ariths_gen/one_bit_circuits/one_bit_components/two_input_one_bit_components.py
View File

@ -29,6 +29,7 @@ class XorGateComponent(TwoInputOneBitCircuit):
super().__init__(a, b, prefix=prefix, name=prefix)
self.out = Bus(self.prefix+"_out", 1)
self.disable_generation = False
obj_and1 = Maji(a, b, ConstantWireValue1(), inverts=[True, True, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), parent_component = parent_component)
self.add_component(obj_and1)
@ -65,6 +66,7 @@ class XnorGateComponent(TwoInputOneBitCircuit):
super().__init__(a, b, prefix=prefix, name=prefix)
self.out = Bus(self.prefix+"_out", 1)
self.disable_generation = True
obj_and1 = Maji(a, b, ConstantWireValue1(), inverts=[True, True, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), parent_component = parent_component)
self.add_component(obj_and1)
@ -108,7 +110,7 @@ class HalfAdder(TwoInputOneBitCircuit):
self.add_component(obj_or)
# cout
obj_and = AndGate(a, b, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=OrGate)), outid=1, parent_component=self)
obj_and = AndGate(a, b, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), outid=1, parent_component=self)
self.add_component(obj_and)
self.out.connect(1, obj_and.out)
@ -200,16 +202,18 @@ class PGLogicBlock(TwoInputOneBitCircuit):
self.out = Bus(self.prefix+"_out", 3)
# PG logic
propagate_or = OrGate(a, b, prefix=self.prefix+"_or"+str(self.get_instance_num(cls=OrGate)), outid=0, parent_component=self)
propagate_or = OrGate (a, b, prefix=self.prefix+"_or" +str(self.get_instance_num(cls=OrGate)), outid=0, parent_component=self)
self.add_component(propagate_or)
generate_and = AndGate(a, b, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), outid=1, parent_component=self)
self.add_component(generate_and)
sum_xor = XorGateComponent(a, b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), outid=2, parent_component=self)
sum_xor = Maji(propagate_or.out, generate_and.out, ConstantWireValue0(), [False, True, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=2, parent_component=self)
self.add_component(sum_xor)
self.out.connect(0, propagate_or.out)
self.out.connect(1, generate_and.out)
self.out.connect(2, sum_xor.out.get_wire(0))
self.out.connect(2, sum_xor.out)
def get_propagate_wire(self):
"""Get output wire carrying propagate signal value.
@ -262,7 +266,13 @@ class HalfSubtractor(TwoInputOneBitCircuit):
# Difference
# XOR gate for calculation of 1-bit difference
difference_xor = XorGateComponent(a=self.a, b=self.b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), outid=0, parent_component=self)
propagate_or = OrGate (a, b, prefix=self.prefix+"_or" +str(self.get_instance_num(cls=OrGate)), outid=0, parent_component=self)
self.add_component(propagate_or)
generate_and = AndGate(a, b, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), outid=1, parent_component=self)
self.add_component(generate_and)
difference_xor = Maji(propagate_or.out, generate_and.out, ConstantWireValue0(), [False, True, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=0, parent_component=self)
self.add_component(difference_xor)
self.out.connect(0, difference_xor.out.get_wire(0))
@ -271,7 +281,7 @@ class HalfSubtractor(TwoInputOneBitCircuit):
not_obj = NotGate(a=self.a, prefix=self.prefix+"_not"+str(self.get_instance_num(cls=NotGate)), parent_component=self)
self.add_component(not_obj)
borrow_and = AndGate(a=not_obj.out, b=self.b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), outid=1, parent_component=self)
borrow_and = AndGate(a=not_obj.out, b=self.b, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), outid=1, parent_component=self)
self.add_component(borrow_and)
self.out.connect(1, borrow_and.out)