ripple cary subtractor
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Vojta Mrazek
parent
e41b4a2f2c
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bc0104de12
@ -18,7 +18,7 @@ class GeneralCircuit():
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The __init__ method fills some mandatory attributes concerning arithmetic circuit
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that are later used for generation into various representations.
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"""
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def __init__(self, prefix: str, name: str, out_N: int, inner_component: bool = False, inputs: list = [], one_bit_circuit: bool = False, signed: bool = False, outname=None, **kwargs):
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def __init__(self, prefix: str, name: str, out_N: int, inner_component: bool = False, inputs: list = [], one_bit_circuit: bool = False, signed: bool = False, signed_out = None, outname=None, **kwargs):
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if prefix == "":
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self.prefix = name
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else:
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@ -41,13 +41,17 @@ class GeneralCircuit():
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if not outname:
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outname = self.prefix+"_out"
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self.out = Bus(outname, out_N, out_bus=True, signed=signed)
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if signed_out is None:
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signed_out = signed
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self.out = Bus(outname, out_N, out_bus=True, signed=signed_out)
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self.components = []
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self._prefixes = [] # TODO rename to fullname and add distinct attr for prefix, name, suffix
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self.circuit_gates = []
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self.circuit_wires = []
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self.signed = signed
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self.signed_out = signed_out
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self.c_data_type = "int64_t" if self.signed is True else "uint64_t"
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self.pyc = None # Python compiled function
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self.kwargs = kwargs
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3
ariths_gen/multi_bit_circuits/subtractors/__init__.py
Normal file
3
ariths_gen/multi_bit_circuits/subtractors/__init__.py
Normal file
@ -0,0 +1,3 @@
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from ariths_gen.multi_bit_circuits.subtractors.ripple_carry_subtractor import (
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UnsignedRippleCarrySubtractor, SignedRippleCarrySubtractor
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)
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@ -0,0 +1,139 @@
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from ariths_gen.wire_components import (
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Bus
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)
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from ariths_gen.core.arithmetic_circuits import (
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GeneralCircuit
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)
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from ariths_gen.one_bit_circuits.one_bit_components import (
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HalfAdder,
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FullAdder
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)
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from ariths_gen.one_bit_circuits.logic_gates import (
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XorGate, NotGate
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)
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from ariths_gen.wire_components.wires import ConstantWireValue1
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class UnsignedRippleCarrySubtractor(GeneralCircuit):
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"""Class representing unsigned ripple carry adder.
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Unsigned ripple carry adder represents N-bit unsigned adder which is composed of
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N one bit fulladders. The first has carry-in set to one and the B input is inverted.
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```
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── ── ── ──
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B3 A3 B2 A2 B1 A1 B0 A0
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│ │ │ │ │ │ │ │
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┌─▼──▼─┐ ┌─▼──▼─┐ ┌─▼──▼─┐ ┌─▼──▼─┐
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│ │ C3│ │ C2│ │ C1│ │ 1
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┌──┤ FA │◄──┤ FA │◄──┤ FA │◄──┤ HA │◄──
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│ │ │ │ │ │ │ │ │
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│ └──────┘ └──────┘ └──────┘ └──────┘
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▼ ▼ ▼ ▼ ▼
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Cout S3 S2 S1 S0
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```
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Description of the __init__ method.
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Args:
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a (Bus): First input bus.
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b (Bus): Second input bus.
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prefix (str, optional): Prefix name of unsigned rcs. Defaults to "".
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name (str, optional): Name of unsigned rcs. Defaults to "u_rcs".
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"""
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def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "u_rcs", **kwargs):
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self.N = max(a.N, b.N)
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super().__init__(inputs=[a, b], prefix=prefix, name=name, out_N=self.N + 1, signed_out=True, **kwargs)
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# Bus sign extension in case buses have different lengths
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self.a.bus_extend(N=self.N, prefix=a.prefix)
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self.b.bus_extend(N=self.N, prefix=b.prefix)
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# Gradual addition of 1-bit adder components
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for input_index in range(self.N):
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b_not = self.add_component(NotGate(self.b.get_wire(input_index), prefix=self.prefix+"_not"+str(input_index)))
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# First adder is a half adder
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if input_index == 0:
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obj_adder = FullAdder(self.a.get_wire(input_index), b_not.out, ConstantWireValue1(), prefix=self.prefix+"_ha")
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# Rest adders are full adders
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else:
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obj_adder = FullAdder(self.a.get_wire(input_index), b_not.out, obj_adder.get_carry_wire(), prefix=self.prefix+"_fa"+str(input_index))
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self.add_component(obj_adder)
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self.out.connect(input_index, obj_adder.get_sum_wire())
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# invert the last carry wire
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self.add_component(NotGate(obj_adder.get_carry_wire(), prefix=self.prefix+"_not_c"+str(self.N-1)))
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self.out.connect(self.N, self.get_previous_component().out)
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class SignedRippleCarrySubtractor(GeneralCircuit):
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"""Class representing signed ripple carry subtractor.
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Signed ripple carry adder represents N-bit signed adder which is composed of
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N one bit adders, where first is a half adder and rest are full adders.
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At last XOR gates are used to ensure proper sign extension.
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Its downside is its long propagation delay the bigger the circuit is.
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```
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__ __ __ __ __ __
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B3 A3 B3 A3 B3 A3 B2 A2 B1 A1 B0 A0
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│ │ │ │ │ │ │ │ │ │ │ │
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┌─▼──▼─┐ ┌─▼──▼─┐ ┌─▼──▼─┐ ┌─▼──▼─┐ ┌─▼──▼─┐ ┌─▼──▼─┐
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│ SIGN │ C4│ SIGN │ C4│ │ C3│ │ C2│ │ C1│ │
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│Extend│◄──│Extend│◄──┤ FA │◄──┤ FA │◄──┤ FA │◄──┤ HA │
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│ 2 │ │ │ │ │ │ │ │ │ │ │
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└──┬───┘ └──┬───┘ └──┬───┘ └──┬───┘ └──┬───┘ └──┬───┘
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▼ ▼ ▼ ▼ ▼ ▼
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S5 S4 S3 S2 S1 S0
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```
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Description of the __init__ method.
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Args:
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a (Bus): First input bus.
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b (Bus): Second input bus.
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prefix (str, optional): Prefix name of signed rca. Defaults to "".
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name (str, optional): Name of signed rca. Defaults to "s_rcs".
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"""
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def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "u_rcs", **kwargs):
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self.N = max(a.N, b.N)
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super().__init__(inputs=[a, b], prefix=prefix, name=name, out_N=self.N + 2, signed=True, **kwargs)
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assert self.a.N == self.b.N, "Both buses must have the same length"
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# Bus sign extension in case buses have different lengths - don't know if works
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self.a.bus_extend(N=self.N, prefix=a.prefix)
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self.b.bus_extend(N=self.N, prefix=b.prefix)
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# Gradual addition of 1-bit adder components
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for input_index in range(self.N):
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b_not = self.add_component(NotGate(self.b.get_wire(input_index), prefix=self.prefix+"_not"+str(input_index)))
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# First adder is a half adder
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if input_index == 0:
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obj_adder = FullAdder(self.a.get_wire(input_index), b_not.out, ConstantWireValue1(), prefix=self.prefix+"_ha")
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# Rest adders are full adders
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else:
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obj_adder = FullAdder(self.a.get_wire(input_index), b_not.out, obj_adder.get_carry_wire(), prefix=self.prefix+"_fa"+str(input_index))
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self.add_component(obj_adder)
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self.out.connect(input_index, obj_adder.get_sum_wire())
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# replicate the last (sign) bit
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obj_adder = FullAdder(self.a.get_wire(self.N - 1), b_not.out, obj_adder.get_carry_wire(), prefix=self.prefix+"_fa_repl_"+str(input_index))
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self.add_component(obj_adder)
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self.out.connect(self.N, self.get_previous_component().get_sum_wire())
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obj_adder = FullAdder(self.a.get_wire(self.N - 1), b_not.out, obj_adder.get_carry_wire(), prefix=self.prefix+"_fa_repl2_"+str(input_index))
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self.add_component(obj_adder)
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self.out.connect(self.N+1, self.get_previous_component().get_sum_wire())
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# invert the last carry wire
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#onot = self.add_component(NotGate(obj_adder.get_carry_wire(), prefix=self.prefix+"_not_c"+str(self.N-1)))
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#self.out.connect(self.N + 1, onot.out)
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@ -44,6 +44,10 @@ from ariths_gen.multi_bit_circuits.adders import (
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SignedCarryIncrementAdder
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)
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from ariths_gen.multi_bit_circuits.subtractors import (
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UnsignedRippleCarrySubtractor, SignedRippleCarrySubtractor
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)
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from ariths_gen.multi_bit_circuits.multipliers import (
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UnsignedDaddaMultiplier,
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UnsignedArrayMultiplier,
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@ -282,6 +286,23 @@ def test_unsigned_add():
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np.testing.assert_array_equal(expected, r)
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def test_unsigned_sub():
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""" Test unsigned subtractor """
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N = 9
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a = Bus(N=N, prefix="a")
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b = Bus(N=N, prefix="b")
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av = np.arange(2**N)
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bv = av.reshape(-1, 1)
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expected = av - bv
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# Non configurable multi-bit subtractors
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for c in [UnsignedRippleCarrySubtractor]:
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sub = c(a, b)
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r = sub(av, bv)
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np.testing.assert_array_equal(expected, r)
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def test_signed_add():
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""" Test signed adders """
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N = 9
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@ -311,6 +332,20 @@ def test_signed_add():
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r = add(av, bv)
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np.testing.assert_array_equal(expected, r)
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def test_signed_sub():
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""" Test signed subtractor """
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N = 4
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a = Bus(N=N, prefix="a")
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b = Bus(N=N, prefix="b")
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av = np.arange(-(2**(N-1)), 2**(N-1))
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bv = av.reshape(-1, 1)
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expected = av - bv
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# Non configurable multi-bit adders
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for c in [SignedRippleCarrySubtractor]:
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sub = c(a, b)
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r = sub(av, bv)
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np.testing.assert_array_equal(expected, r)
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def test_mac():
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class MAC(GeneralCircuit):
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