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Static write FA to PGAdder
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This commit is contained in:
Lukas Plevac 2025-01-19 19:10:26 +01:00
parent 6c8c791fb5
commit e662c52e75
2 changed files with 13 additions and 6 deletions
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2
ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py
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@ -26,8 +26,6 @@ class FullAdder(ThreeInputOneBitCircuit):
name (str, optional): Name of full adder. Defaults to "fa".
"""
use_verilog_instance = False
disable_generation = False
def __init__(self, a: Wire = Wire(name="a"), b: Wire = Wire(name="b"), c: Wire = Wire(name="cin"), prefix: str = "", name: str = "fa"):
super().__init__(a, b, c, prefix=prefix, name=name)
# 2 wires for component's bus output (sum, cout)

17
ariths_gen/one_bit_circuits/one_bit_components/two_input_one_bit_components.py
View File

@ -1,5 +1,4 @@
from ariths_gen.core.one_bit_circuits import TwoInputOneBitCircuit
from .three_input_one_bit_components import FullAdder
from ariths_gen.one_bit_circuits.logic_gates import AndGate, NandGate, OrGate, NorGate, NotGate
from ariths_gen.one_bit_circuits import Maji
from ariths_gen.wire_components import Wire, Bus
@ -209,12 +208,22 @@ class partialAdder(TwoInputOneBitCircuit):
generate_and = AndGate(a, b, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), outid=1, parent_component=self)
self.add_component(generate_and)
fa = FullAdder(a, b, cin, prefix=self.prefix+"_fa" +str(self.get_instance_num(cls=FullAdder)))
self.add_component(fa)
##
# FA
obj_maji1 = Maji(cin, a, b, [True, False, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=2, parent_component=self)
self.add_component(obj_maji1)
# cout
obj_maji2 = Maji(cin, a, b, [False, False, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=2, parent_component=self)
self.add_component(obj_maji2)
# sum
obj_maji3 = Maji(cin, obj_maji1.out, obj_maji2.out, [False, False, True], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=2, parent_component=self)
self.add_component(obj_maji3)
self.out.connect(0, propagate_or.out)
self.out.connect(1, generate_and.out)
self.out.connect(2, fa.get_sum_wire())
self.out.connect(2, obj_maji3.out)
def get_propagate_wire(self):
"""Get output wire carrying propagate signal value.