Vojta Mrazek
35240abc63
fix bug in python interpretation
2023-02-22 09:43:24 +01:00
Jan Klhůfek
56c86c13ca
New multipliers ( #13 )
...
* #10 CGP Circuits as inputs (#11 )
* CGP Circuits as inputs
* #10 support of signed output in general circuit
* input as output works
* output connected to input (c)
* automated verilog testing
* output rename
* Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup.
* Typos fix and code cleanup.
* Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.
* Updated automated testing scripts.
* Small bugfix in python code generation (I initially thought this line is useless).
* Updated generated circuits folder.
Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
2022-04-17 16:00:00 +02:00
Honza
b1ddc8c387
Small bugfix in python code generation (I initially thought this line is useless).
2022-04-17 13:25:10 +02:00
Honza
c0dcf42499
Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.
2022-04-17 13:04:17 +02:00
Honza
9e186d10ed
Typos fix and code cleanup.
2022-02-18 17:24:09 +01:00
Honza
6f05db002e
Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup.
2022-02-18 17:00:31 +01:00
Vojta Mrazek
3c47407f80
output rename
2022-02-07 11:29:12 +01:00
Vojta Mrazek
ee8621ef4d
output connected to input (c)
2022-02-02 12:53:18 +01:00
Vojta Mrazek
dc705106b4
input as output works
2022-02-02 11:19:32 +01:00
Vojta Mrazek
1e44c2e3dc
#10 CGP Circuits as inputs ( #11 )
...
* CGP Circuits as inputs
* #10 support of signed output in general circuit
2022-02-01 13:23:26 +01:00
Honza
13c085f169
Fixed a small bug – missing ending semicolon in generation of library desired HA/FA to Verilog. Added script for generation of AX multipliers.
2022-01-13 13:11:24 +01:00
Vojta Mrazek
d641595c3e
Support of PDK in HA and FA
2022-01-13 12:37:09 +01:00
Honza
18b44226d8
Small bugfixes and removal of redundant code.
2022-01-07 20:36:51 +01:00
Honza
d9b56e8a00
Fixed generation of unsigned variants of BAM and TM multipliers. Signed versions don't guarantee correct funcionality atm.
2022-01-06 19:23:56 +01:00
Honza
9aa0fb1858
Added broken array multiplier and truncated multiplier implementations. Tried testing them, but seems buggy. Needs further work.
2022-01-06 06:39:58 +01:00
Honza
f830029c54
Added truncated multiplier circuit implementation. Needs testing.
2022-01-04 03:13:21 +01:00
Honza
c8ed08691f
Updated functionality of the extend_bus method.
2021-11-16 00:02:52 +01:00
Honza
2083ed35a1
Returned inner circuit's input buses extension feature back to its original form.
2021-11-15 22:58:34 +01:00
honzastor
f582ee729e
Updated generation of hierarchical circuits to allow proper naming consistency between the subcomponent modules and their corresponding invocations.
2021-10-25 01:11:34 +02:00
honzastor
5d41997560
Added assertion checks for the same input bus lengths when initializing arithmetic circuits.
2021-10-24 18:48:00 +02:00
honzastor
d41c5f3c94
Updated exportation of signed arithmetic circuits to python representation. Also unified some methods from arithmetic_circuit.py into general_circuit.py.
2021-10-10 22:15:13 +02:00
honzastor
cfb5bba3ec
Bitwise and operation fix.
2021-10-10 00:02:58 +02:00
honzastor
16c1757bc3
Added signedness support for the output C code representation. Also modified the testing scripts and the chr2c.py converter accordingly and did some documentation changes (even made a small change in readme.md). Signedness support for the output python representation is TBD.
2021-10-09 23:45:54 +02:00
Vojta Mrazek
152a6b1583
Python eval ( #4 )
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* #3 basic clean up arithmetic circuit and general circuit
* #3 implementation of python generator
* #3 pytest in actions
* #3 pytest in actions fix
2021-10-04 11:58:28 +02:00
Vojta Mrazek
995107eecc
Removing of file closing
2021-09-23 08:50:18 +02:00
honzastor
eba0a7a938
Made some minor changes concerning proper exportation of multiplier circuits.
2021-09-09 13:57:36 +02:00
honzastor
e16de78c2b
Updated logic behind generating export representations, mainly focused around circuit and its buses and subcomponents namings.
2021-09-07 17:39:39 +02:00
Vojta Mrazek
8c0f24cd2d
General MAC circuit
2021-09-06 12:52:13 +02:00
Vojta Mrazek
a4dca24fc2
CGP format minor
2021-06-23 14:09:46 +02:00
Vojta Mrazek
0a487ee699
CGP format
2021-06-23 14:08:49 +02:00
Vojta Mrazek
c6e542231c
CGP tests; reversed output order
2021-06-23 13:43:58 +02:00
Vojta Mrazek
cfe0ca6b4b
Automated testing, preparing the package for publishing ( #1 )
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* automated pandoc deploy
* automated pandoc deploy (v2)
* automated pandoc deploy (v2)
* automated pdoc deploy (v3)
* automated pdoc deploy (v4)
* automated pdoc deploy (v5)
* automated pdoc deploy (v5)
* prepare for python project
* 8-bit testing
* 8-bit testing
* 8-bit testing (v2)
* 8-bit testing (v3)
* update of sign
2021-06-18 12:38:11 +02:00
honzastor
e5f2dd893a
Fixed proper generated circuits names (mistakenly named cska as csa).
2021-04-28 21:39:58 +02:00
honzastor
0f66c5a2e9
Fixed proper connections in submodules instantiation in hierarchical Verilog generation. Sample generated circuits were also accordingly updated.
2021-04-23 11:49:24 +02:00
honzastor
670ba45ee5
Generated sample circuits for various representations. Updated C code circuits testing simulations and did some cleanup.
2021-04-23 02:44:14 +02:00
honzastor
ad1c6ec557
Updated circuits documentation.
2021-04-21 13:42:07 +02:00
honzastor
8e950fc51f
Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits.
2021-04-21 11:33:07 +02:00
honzastor
068def0226
Added documentation of classes methods.
2021-04-06 01:39:11 +02:00
honzastor
a336a683e7
Added some code documentation and updated git action to generate it.
2021-03-31 04:40:54 +02:00
Jan Klhůfek
82d2d02ef5
Delete ariths_gen/one_bit_circuits/logic_gates/__pycache__ directory
2021-03-30 03:13:15 +02:00
Jan Klhůfek
debef13087
Delete ariths_gen/one_bit_circuits/one_bit_components/__pycache__ directory
2021-03-30 03:13:04 +02:00
Jan Klhůfek
9a4c2c4dd7
Delete ariths_gen/multi_bit_circuits/multipliers/__pycache__ directory
2021-03-30 03:12:43 +02:00
Jan Klhůfek
d27fbf7088
Delete ariths_gen/multi_bit_circuits/adders/__pycache__ directory
2021-03-30 03:12:31 +02:00
Jan Klhůfek
669920b0d5
Delete ariths_gen/wire_components/__pycache__ directory
2021-03-30 03:12:11 +02:00
Jan Klhůfek
1e2ae53df5
Delete ariths_gen/one_bit_circuits/__pycache__ directory
2021-03-30 03:11:57 +02:00
Jan Klhůfek
e28574a7c9
Delete ariths_gen/multi_bit_circuits/__pycache__ directory
2021-03-30 03:11:38 +02:00
Jan Klhůfek
87105eaaa6
Delete ariths_gen/core/__pycache__ directory
2021-03-30 03:11:13 +02:00
Jan Klhůfek
86479086c0
Delete ariths_gen/__pycache__ directory
2021-03-30 03:11:03 +02:00
honzastor
69e2514852
Updated project's structure. Renamed class names to properly fit Python naming convention. TBD: proper documentation.
2021-03-30 03:04:48 +02:00
