Lukas Plevac c9c99fbb11 Optimalize MUX

2024-11-16 20:54:41 +01:00

..

core

Fully working xorGateComponent

2024-10-10 13:33:09 +02:00

multi_bit_circuits

Fix mux with wrong gate ordering

2024-11-14 15:15:17 +01:00

one_bit_circuits

Optimalize MUX

2024-11-16 20:54:41 +01:00

wire_components

reconnected wire was not identified as a bus

2024-07-22 15:10:21 +02:00

__init__.py

Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.

2023-02-24 11:13:46 +01:00

pdk.py

Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated).

2023-03-22 17:57:51 +01:00