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dissertation_thesis
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ariths-gen-mig
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ariths-gen-mig
/
ariths_gen
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Vojta Mrazek
44e0a920d1
MUX support of constant values
2023-03-24 12:11:42 +01:00
..
core
Bugfix in conditional statement.
2023-03-22 18:14:55 +01:00
multi_bit_circuits
Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.
2023-02-24 11:13:46 +01:00
one_bit_circuits
MUX support of constant values
2023-03-24 12:11:42 +01:00
wire_components
accepts a wire as a bus
2023-03-23 13:39:32 +01:00
__init__.py
Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.
2023-02-24 11:13:46 +01:00
pdk.py
Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated).
2023-03-22 17:57:51 +01:00
