dissertation_thesis/ariths-gen-mig
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ariths-gen-mig/ariths_gen
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Lukas Plevac 4eb65e10da
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All working muls and adders
2024-10-17 19:11:02 +02:00
..
core
Fully working xorGateComponent
2024-10-10 13:33:09 +02:00
multi_bit_circuits
Fully working xorGateComponent
2024-10-10 13:33:09 +02:00
one_bit_circuits
All working muls and adders
2024-10-17 19:11:02 +02:00
wire_components
reconnected wire was not identified as a bus
2024-07-22 15:10:21 +02:00
__init__.py
Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.
2023-02-24 11:13:46 +01:00
pdk.py
Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated).
2023-03-22 17:57:51 +01:00