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v1.0

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• e662c52e75 Static write FA to PGAdder main Lukas Plevac 2025-01-19 19:10:26 +01:00
• 6c8c791fb5 Code generation fix Lukas Plevac 2025-01-19 18:34:06 +01:00
• db25df54cd unexpected keyword argument 'parent_component' Lukáš Plevač 2025-01-15 19:33:13 +01:00
• cf4a6ccc52 Incorect FA instance create Lukáš Plevač 2025-01-15 19:31:12 +01:00
• aefc20693a Full adder missing import Lukáš Plevač 2025-01-15 19:28:29 +01:00
• 395750eac5 Imprt missing full adder Lukáš Plevač 2025-01-15 19:23:47 +01:00
• d0501238f8 GCP PGA ADDER Lukáš Plevač 2025-01-06 13:03:21 +01:00
• 8adba05ba4 Update readme Lukas Plevac 2024-11-16 20:54:51 +01:00
• c9c99fbb11 Optimalize MUX Lukas Plevac 2024-11-16 20:54:41 +01:00
• db231dd7f7 Simple generate example Lukas Plevac 2024-11-16 20:46:26 +01:00
• e576a9fd81 Aktualizovat README.md Lukáš Plevač 2024-11-14 15:48:07 +01:00
• bb94958118 Fix unsigned mul test Lukáš Plevač 2024-11-14 15:22:46 +01:00
• 5bb50a325f Remove iverilog from pipe Lukáš Plevač 2024-11-14 15:19:54 +01:00
• 975ab01a1c Fixing pipeline Lukáš Plevač 2024-11-14 15:18:50 +01:00
• c476479827 Fix mux with wrong gate ordering Lukáš Plevač 2024-11-14 15:15:17 +01:00
• 4eb65e10da All working muls and adders Lukas Plevac 2024-10-17 19:11:02 +02:00
• 09a12f3df7 Fully working xorGateComponent Lukas Plevac 2024-10-10 13:33:09 +02:00
• c61244c966 Fixed RCA by test Lukas Plevac 2024-10-08 14:28:38 +02:00
• 6132c3c449 Optimalized MAJ implementation for adders Lukas Plevac 2024-10-08 13:39:48 +02:00
• ad9f62e3de Added support for MIG excluded xor and xnor gate Lukas Plevac 2024-10-07 15:19:55 +02:00
• 63a11f244c
  Merge pull request #27 from ehw-fit/devel Jan Klhůfek 2024-10-03 12:39:02 +02:00
• 616efb25db workflow documentation Vojta 2024-10-03 08:20:24 +02:00
• 813f111df7 Merge branch 'devel' of github.com:ehw-fit/ariths-gen into devel Vojta 2024-10-03 08:19:27 +02:00
• c1e8680e83 CGP with more than 26 inputs naming Vojta 2024-10-03 08:18:49 +02:00
• 397876b265
  Merge pull request #26 from ehw-fit/devel Vojta Mrazek 2024-10-02 21:30:58 +02:00
• e804265a7b Updated git actions. honzastor 2024-10-02 14:56:52 +02:00
• 03212a62f5 Actions fix honzastor 2024-10-01 18:47:24 +02:00
• b87f8350fc Added ripple borrow subtractor circuit and updated automated testing. honzastor 2024-10-01 18:42:11 +02:00
• bc95444995 reconnected wire was not identified as a bus Vojta Mrazek 2024-07-22 15:10:21 +02:00
• 04cd3e44d3 bug in cgp indexes with constant wires, they were encouted Vojta Mrazek 2024-07-22 15:09:50 +02:00
• f34471bfe3 signed version of python code Vojta Mrazek 2024-07-18 13:16:15 +02:00
• 4cd1189d4a CGP circuit accepts BUS inputs Vojta Mrazek 2024-07-18 13:15:56 +02:00
• bc0104de12 ripple cary subtractor Vojta Mrazek 2024-07-09 09:22:11 +02:00
• e41b4a2f2c Merge branch 'devel' of github.com:ehw-fit/ariths-gen into devel Vojta Mrazek 2024-07-08 11:31:30 +02:00
• c480eeacf9 popcount parent component Vojta Mrazek 2024-07-08 11:29:25 +02:00
• ce36ebf77b Fixed hierarchical BLIF generation for popcount_compare. honzastor 2024-04-17 18:47:41 +02:00
• f4b816fc09 Fix for workflow tests honzastor 2024-04-14 16:36:45 +02:00
• 6003886eb7 Fixed hierarchical Verilog generation of popcount compare. BLIF probably needs a similar treatment, TBD later honzastor 2024-04-14 16:29:10 +02:00
• 97e79b93da Big code cleanup and some fixes. Hierarchical generation for popcount seems problematic. It seems bus connections are the issue. honzastor 2024-04-13 17:04:03 +02:00
• 739d5fafce Added documentation to Recursive multiplier and hopefully fixed some issues with popcount output generation. honzastor 2024-04-08 21:37:34 +02:00
• 4e331f0525 popcount with variable sizes Vojta Mrazek 2024-04-08 13:48:25 +02:00
• 211dd49fb5
  Merge pull request #25 from ehw-fit/popcount Jan Klhůfek 2024-04-05 12:40:39 +02:00
• 0180735dd5 workflow to node.js 20 Vojta Mrazek 2024-04-05 11:27:41 +02:00
• 84a41ad93c test unique #21 Vojta Mrazek 2024-04-05 11:25:37 +02:00
• 77724ad115 workflow update Vojta Mrazek 2024-04-05 11:21:42 +02:00
• 128b1309a1 popcount fixes Vojta Mrazek 2024-04-05 09:24:03 +02:00
• 8468c5b8fd
  Merge pull request #24 from ehw-fit/devel Vojta Mrazek 2024-04-05 09:19:26 +02:00
• 1219d7bec5
  Merge branch 'popcount' into devel Vojta Mrazek 2024-04-05 09:19:04 +02:00
• 2cf7b921ea Popcount implementation Vojta Mrazek 2024-04-05 08:46:02 +02:00
• da733cf44e Added instantiation of wires and buses from inputs. Hopefully fixed now. honzastor 2024-03-28 00:06:53 +01:00
• cd3441ff00 Removed error tests from overall testing. honzastor 2024-03-27 23:44:34 +01:00
• 21a6437eb8 Additional type hint fix. honzastor 2024-03-27 23:19:40 +01:00
• 73101eb055 Type hint bugfix for pytest. honzastor 2024-03-27 23:10:06 +01:00
• d013a40145 Added unsigned recursive multiplier and made some bugfixes. honzastor 2024-03-27 23:00:13 +01:00
• 2e1694ccd5 popcount and compare Vojta Mrazek 2024-03-22 14:19:23 +01:00
• 7e1112cf81 Added individual input bus attributes to CGP Circuit objects to allow for the generation of output CGP representation. honzastor 2024-03-06 00:42:12 +01:00
• f853a46703 CGP circuit checks Vojta Mrazek 2023-04-13 12:09:07 +02:00
• a44b0638a1 Implementation of QuAd approximate adder Vojta Mrazek 2023-03-28 13:55:58 +02:00
• a4741db191 connection checks (asserts) Vojta Mrazek 2023-03-28 11:16:55 +02:00
• 44e0a920d1 MUX support of constant values Vojta Mrazek 2023-03-24 12:11:42 +01:00
• 49bbc86a0f accepts a wire as a bus Vojta Mrazek 2023-03-23 13:39:32 +01:00
• 363e402e16 workflow: docs Vojta Mrazek 2023-03-23 08:00:37 +01:00
• d16ab17512
  Merge pull request #20 from ehw-fit/main Vojta Mrazek 2023-03-23 07:53:54 +01:00
• 7cf34d04f3 Bugfix in conditional statement. honzastor 2023-03-22 18:14:55 +01:00
• b88c502343 Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated). honzastor 2023-03-22 17:57:51 +01:00
• cf747918bf
  Merge pull request #19 from ehw-fit/devel Jan Klhůfek 2023-02-24 14:12:40 +01:00
• bb4c6d35a7 page deploy Vojta Mrazek 2023-02-24 13:41:36 +01:00
• 6bbe9eb253
  Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers. (#18) Jan Klhůfek 2023-02-24 13:34:35 +01:00
• d52e67bb25 Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers. honzastor 2023-02-24 11:13:46 +01:00
• 2d7e157453
  Merge pull request #17 from ehw-fit/devel Jan Klhůfek 2023-02-22 18:59:31 +01:00
• 283f9c79f5
  Merge branch 'main' into devel Vojta Mrazek 2023-02-22 12:12:20 +01:00
• d022195e48
  Workflow (#16) Vojta Mrazek 2023-02-22 12:08:21 +01:00
• da4347148c workflow python 3.6 version Vojta Mrazek 2023-02-22 10:00:32 +01:00
• 60c4d3d24e workflow python 3.6 version Vojta Mrazek 2023-02-22 09:55:19 +01:00
• 6dd69c5aaa Merge branch 'devel' of github.com:ehw-fit/ariths-gen into devel Vojta Mrazek 2023-02-22 09:52:34 +01:00
• 43b3d65463 workflow modification, bus indexing Vojta Mrazek 2023-02-22 09:52:06 +01:00
• 71a1d45045
  string description (#15) Vojta Mrazek 2023-02-22 09:45:14 +01:00
• 35240abc63 fix bug in python interpretation Vojta Mrazek 2023-02-22 09:43:24 +01:00
• a4a48dea57
  Create codeql-analysis.yml (#14) Vojta Mrazek 2022-05-26 10:08:35 +02:00
• 56c86c13ca
  New multipliers (#13) Jan Klhůfek 2022-04-17 16:00:00 +02:00
• f17e87738e Updated generated circuits folder. Honza 2022-04-17 13:41:32 +02:00
• b1ddc8c387 Small bugfix in python code generation (I initially thought this line is useless). Honza 2022-04-17 13:25:10 +02:00
• 5d2f4e07e7 Updated automated testing scripts. Honza 2022-04-17 13:06:46 +02:00
• c0dcf42499 Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats. Honza 2022-04-17 13:04:17 +02:00
• 5475e3aa75
  Added ArXiv badge and paper reference (#12) Jan Klhůfek 2022-03-25 07:19:38 +01:00
• 9e186d10ed Typos fix and code cleanup. Honza 2022-02-18 17:24:09 +01:00
• 6f05db002e Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup. Honza 2022-02-18 17:00:31 +01:00
• 3c47407f80 output rename Vojta Mrazek 2022-02-07 11:29:12 +01:00
• 1c2efef024 automated verilog testing Vojta Mrazek 2022-02-02 13:19:54 +01:00
• ee8621ef4d output connected to input (c) Vojta Mrazek 2022-02-02 12:53:18 +01:00
• dc705106b4 input as output works Vojta Mrazek 2022-02-02 11:19:32 +01:00
• 1e44c2e3dc
  #10 CGP Circuits as inputs (#11) Vojta Mrazek 2022-02-01 13:23:26 +01:00
• d445f9e3c7
  Merge pull request #9 from ehw-fit/devel v1.0 Vojta Mrazek 2022-01-13 16:16:02 +01:00
• 5646334b7f workflow axmult typo Vojta Mrazek 2022-01-13 16:11:48 +01:00
• aeacd72d24 Readme, axmults in workflow Vojta Mrazek 2022-01-13 16:10:51 +01:00
• 13c085f169 Fixed a small bug – missing ending semicolon in generation of library desired HA/FA to Verilog. Added script for generation of AX multipliers. Honza 2022-01-13 13:11:24 +01:00
• d641595c3e Support of PDK in HA and FA Vojta Mrazek 2022-01-13 12:37:09 +01:00
• 18b44226d8 Small bugfixes and removal of redundant code. Honza 2022-01-07 20:36:51 +01:00
• d9b56e8a00 Fixed generation of unsigned variants of BAM and TM multipliers. Signed versions don't guarantee correct funcionality atm. Honza 2022-01-06 19:23:56 +01:00
• 2075c0edf5 Another fix Honza 2022-01-06 06:46:11 +01:00