Vojta Mrazek bc95444995 reconnected wire was not identified as a bus

2024-07-22 15:10:21 +02:00

..

core

bug in cgp indexes with constant wires, they were encouted

2024-07-22 15:09:50 +02:00

multi_bit_circuits

ripple cary subtractor

2024-07-09 09:22:11 +02:00

one_bit_circuits

Fixed hierarchical BLIF generation for popcount_compare.

2024-04-17 18:47:41 +02:00

wire_components

reconnected wire was not identified as a bus

2024-07-22 15:10:21 +02:00

__init__.py

Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.

2023-02-24 11:13:46 +01:00

pdk.py

Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated).

2023-03-22 17:57:51 +01:00