Code generation fix

2025-01-19 18:34:06 +01:00 · 2025-01-19 18:34:06 +01:00 · 6c8c791fb5
commit 6c8c791fb5
parent db25df54cd
1 changed files with 1 additions and 0 deletions
--- a/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py
+++ b/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py
@ -26,6 +26,7 @@ class FullAdder(ThreeInputOneBitCircuit):
        name (str, optional): Name of full adder. Defaults to "fa".
    """
    use_verilog_instance = False
+    disable_generation   = False

    def __init__(self, a: Wire = Wire(name="a"), b: Wire = Wire(name="b"), c: Wire = Wire(name="cin"), prefix: str = "", name: str = "fa"):
        super().__init__(a, b, c, prefix=prefix, name=name)