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from ariths_gen.core.one_bit_circuits import TwoInputOneBitCircuit
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from ariths_gen.one_bit_circuits.logic_gates import AndGate, NandGate, OrGate, NorGate, NotGate
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from ariths_gen.one_bit_circuits import Maji
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from ariths_gen.wire_components import Wire, Bus
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from ariths_gen.wire_components.wires import ConstantWireValue0, ConstantWireValue1
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class XorGateComponent(TwoInputOneBitCircuit):
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"""Class representing two input XOR gate.
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```
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┌──────┐
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───►│ =1 │
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│ ├─►
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───►│ │
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└──────┘
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```
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Description of the __init__ method.
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Args:
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a (Wire): First input wire.
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b (Wire): Second input wire.
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prefix (str, optional): Prefix name of XOR gate. Defaults to "".
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outid (int, optional): Index of output wire. Defaults to 0.
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parent_component (object, optional) Object of upper component of which XOR gate is a subcomponent. Defaults to None.
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"""
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def __init__(self, a: Wire, b: Wire, prefix: str = "", outid: int = 0, parent_component: object = None):
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super().__init__(a, b, prefix=prefix, name=prefix)
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self.out = Bus(self.prefix+"_out", 1)
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self.disable_generation = False
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obj_and1 = Maji(a, b, ConstantWireValue1(), inverts=[True, True, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), parent_component = parent_component)
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self.add_component(obj_and1)
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obj_and2 = Maji(a, b, ConstantWireValue1(), inverts=[False, False, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), parent_component = parent_component)
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self.add_component(obj_and2)
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# sum
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obj_and3 = Maji(obj_and1.out, obj_and2.out, ConstantWireValue0(), [False, False, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=outid, parent_component=parent_component)
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self.add_component(obj_and3)
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self.out.connect(0, obj_and3.out)
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class XnorGateComponent(TwoInputOneBitCircuit):
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"""Class representing two input XNOR gate.
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```
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┌──────┐
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───►│ =1 │
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│ │O──►
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───►│ │
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└──────┘
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```
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Description of the __init__ method.
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Args:
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a (Wire): First input wire.
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b (Wire): Second input wire.
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prefix (str, optional): Prefix name of XNOR gate. Defaults to "".
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outid (int, optional): Index of output wire. Defaults to 0.
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parent_component (object, optional) Object of upper component of which XNOR gate is a subcomponent. Defaults to None.
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"""
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def __init__(self, a: Wire, b: Wire, prefix: str = "", outid: int = 0, parent_component: object = None):
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super().__init__(a, b, prefix=prefix, name=prefix)
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self.out = Bus(self.prefix+"_out", 1)
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self.disable_generation = True
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obj_and1 = Maji(a, b, ConstantWireValue1(), inverts=[True, True, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), parent_component = parent_component)
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self.add_component(obj_and1)
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obj_and2 = Maji(a, b, ConstantWireValue1(), inverts=[False, False, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), parent_component = parent_component)
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self.add_component(obj_and2)
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# sum
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obj_and3 = Maji(obj_and1.out, obj_and2.out, ConstantWireValue1(), [True, True, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=outid, parent_component=parent_component)
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self.add_component(obj_and3)
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self.out.connect(0, obj_and3.out)
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class HalfAdder(TwoInputOneBitCircuit):
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"""Class representing two input one bit half adder.
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```
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┌──────┐
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───►│ ├─► Sum
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│ │
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───►│ ├─► Cout
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└──────┘
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```
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Description of the __init__ method.
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Args:
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a (Wire, optional): First input wire. Defaults to Wire(name="a").
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b (Wire, optional): Second input wire. Defaults to Wire(name="b").
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prefix (str, optional): Prefix name of half adder. Defaults to "".
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name (str, optional): Name of half adder. Defaults to "ha".
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"""
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use_verilog_instance = False
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def __init__(self, a: Wire = Wire(name="a"), b: Wire = Wire(name="b"), prefix: str = "", name: str = "ha"):
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super().__init__(a, b, prefix=prefix, name=name)
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# 2 wires for component's bus output (sum, cout)
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self.out = Bus(self.prefix+"_out", 2)
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obj_or = OrGate (a, b, prefix=self.prefix+"_or" +str(self.get_instance_num(cls=OrGate)), outid=0, parent_component=self)
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self.add_component(obj_or)
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# cout
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obj_and = AndGate(a, b, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), outid=1, parent_component=self)
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self.add_component(obj_and)
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self.out.connect(1, obj_and.out)
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# sum
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obj_maji = Maji(obj_or.out, obj_and.out, ConstantWireValue0(), [False, True, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=0, parent_component=self)
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self.add_component(obj_maji)
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self.out.connect(0, obj_maji.out)
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def get_sum_wire(self):
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"""Get output wire carrying sum value.
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Returns:
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Wire: Return sum wire.
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"""
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return self.out.get_wire(0)
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def get_carry_wire(self):
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"""Get output wire carrying carry out value.
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Returns:
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Wire: Return carry out wire.
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"""
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return self.out.get_wire(1)
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def get_init_v_flat(self):
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""" support of custom PDK """
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if not self.use_verilog_instance:
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return super().get_init_v_flat()
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return " " + self.use_verilog_instance.format(
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**{
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"unit": self.prefix,
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"wirea": f"1'b{self.a.value}" if self.a.is_const() else self.a.name,
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"wireb": f"1'b{self.b.value}" if self.b.is_const() else self.b.name,
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"wireys": self.get_sum_wire().prefix,
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"wireyc": self.get_carry_wire().prefix,
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}) + ";\n"
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def get_self_init_v_hier(self):
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""" support of custom PDK """
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if not self.use_verilog_instance:
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return super().get_self_init_v_hier()
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unique_out_wires = []
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for o in self.out.bus:
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unique_out_wires.append(o.name+"_outid"+str(self.out.bus.index(o))) if o.is_const() or o.name in [self.a.name, self.b.name] else unique_out_wires.append(o.name)
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return " " + self.use_verilog_instance.format(
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**{
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"unit": self.prefix,
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"wirea": self.a.name,
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"wireb": self.b.name,
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"wireys": unique_out_wires[0],
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"wireyc": unique_out_wires[1],
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}) + ";\n"
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def get_circuit_v(self):
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""" support of custom PDK """
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if not self.use_verilog_instance:
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return super().get_circuit_v()
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return f"{self.get_prototype_v_hier()}" + \
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f"{self.get_self_init_v_hier()}" + \
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f"endmodule"
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class partialAdder(TwoInputOneBitCircuit):
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"""Class representing two input one bit propagate/generate logic block.
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```
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┌──────┐
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A ───►│ ├─► P
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B ───►│ ├─► G
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Cin ───►│ ├─► S
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└──────┘
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```
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Description of the __init__ method.
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Args:
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a (Wire, optional): First input wire. Defaults to Wire(name="a").
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b (Wire, optional): Second input wire. Defaults to Wire(name="b").
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prefix (str, optional): Prefix name of pg logic block. Defaults to "".
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name (str, optional): Name of pg logic block. Defaults to "pg_logic".
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"""
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def __init__(self, a: Wire = Wire(name="a"), b: Wire = Wire(name="b"), cin: Wire = Wire(name="cin"), prefix: str = "", name: str = "pg_logic"):
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super().__init__(a, b, prefix=prefix, name=name)
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# 3 wires for component's bus output (propagate, generate, sum)
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self.out = Bus(self.prefix+"_out", 3)
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# PG logic
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propagate_or = OrGate (a, b, prefix=self.prefix+"_or" +str(self.get_instance_num(cls=OrGate)), outid=0, parent_component=self)
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self.add_component(propagate_or)
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generate_and = AndGate(a, b, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), outid=1, parent_component=self)
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self.add_component(generate_and)
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fa = FullAdder(self, a, b, cin, prefix=self.prefix+"_fa" +str(self.get_instance_num(cls=FullAdder)), parent_component=self)
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self.add_component(fa)
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self.out.connect(0, propagate_or.out)
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self.out.connect(1, generate_and.out)
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self.out.connect(2, fa.get_sum_wire())
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def get_propagate_wire(self):
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"""Get output wire carrying propagate signal value.
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Returns:
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Wire: Return propagate wire.
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"""
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return self.out.get_wire(0)
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def get_generate_wire(self):
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"""Get output wire carrying generate signal value.
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Returns:
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Wire: Return generate wire.
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"""
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return self.out.get_wire(1)
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def get_sum_wire(self):
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"""Get output wire carrying sum value.
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Returns:
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Wire: Return sum wire.
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"""
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return self.out.get_wire(2)
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class HalfSubtractor(TwoInputOneBitCircuit):
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"""Class representing two input one bit half subtractor.
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```
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┌──────┐
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───►│ ├─► Difference
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│ │
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───►│ ├─► Bout
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└──────┘
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```
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Description of the __init__ method.
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Args:
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a (Wire, optional): First input wire. Defaults to Wire(name="a").
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b (Wire, optional): Second input wire. Defaults to Wire(name="b").
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prefix (str, optional): Prefix name of half subtractor adder. Defaults to "".
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name (str, optional): Name of half subtractor adder. Defaults to "hs".
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"""
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def __init__(self, a: Wire = Wire(name="a"), b: Wire = Wire(name="b"), prefix: str = "", name: str = "hs"):
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super().__init__(a, b, prefix=prefix, name=name)
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# 2 wires for component's bus output (difference, bout)
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self.out = Bus(self.prefix+"_out", 2)
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# Difference
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# XOR gate for calculation of 1-bit difference
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propagate_or = OrGate (a, b, prefix=self.prefix+"_or" +str(self.get_instance_num(cls=OrGate)), outid=0, parent_component=self)
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self.add_component(propagate_or)
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generate_and = AndGate(a, b, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), outid=1, parent_component=self)
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self.add_component(generate_and)
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difference_xor = Maji(propagate_or.out, generate_and.out, ConstantWireValue0(), [False, True, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=0, parent_component=self)
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self.add_component(difference_xor)
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self.out.connect(0, difference_xor.out.get_wire(0))
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# Bout
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# NOT and AND gates for calculation of 1-bit borrow out
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not_obj = NotGate(a=self.a, prefix=self.prefix+"_not"+str(self.get_instance_num(cls=NotGate)), parent_component=self)
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self.add_component(not_obj)
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borrow_and = AndGate(a=not_obj.out, b=self.b, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), outid=1, parent_component=self)
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self.add_component(borrow_and)
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self.out.connect(1, borrow_and.out)
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def get_difference_wire(self):
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"""Get output wire carrying difference value.
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Returns:
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Wire: Return difference wire.
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"""
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return self.out.get_wire(0)
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def get_borrow_wire(self):
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"""Get output wire carrying borrow out value.
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Returns:
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Wire: Return borrow out wire.
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"""
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return self.out.get_wire(1)
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from ariths_gen.core.one_bit_circuits import TwoInputOneBitCircuit, FullAdder
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from ariths_gen.one_bit_circuits.logic_gates import AndGate, NandGate, OrGate, NorGate, NotGate
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from ariths_gen.one_bit_circuits import Maji
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from ariths_gen.wire_components import Wire, Bus
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from ariths_gen.wire_components.wires import ConstantWireValue0, ConstantWireValue1
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class XorGateComponent(TwoInputOneBitCircuit):
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"""Class representing two input XOR gate.
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```
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┌──────┐
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───►│ =1 │
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│ ├─►
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───►│ │
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└──────┘
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```
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Description of the __init__ method.
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Args:
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a (Wire): First input wire.
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b (Wire): Second input wire.
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prefix (str, optional): Prefix name of XOR gate. Defaults to "".
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outid (int, optional): Index of output wire. Defaults to 0.
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parent_component (object, optional) Object of upper component of which XOR gate is a subcomponent. Defaults to None.
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"""
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def __init__(self, a: Wire, b: Wire, prefix: str = "", outid: int = 0, parent_component: object = None):
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super().__init__(a, b, prefix=prefix, name=prefix)
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self.out = Bus(self.prefix+"_out", 1)
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self.disable_generation = False
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obj_and1 = Maji(a, b, ConstantWireValue1(), inverts=[True, True, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), parent_component = parent_component)
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self.add_component(obj_and1)
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obj_and2 = Maji(a, b, ConstantWireValue1(), inverts=[False, False, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), parent_component = parent_component)
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self.add_component(obj_and2)
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# sum
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obj_and3 = Maji(obj_and1.out, obj_and2.out, ConstantWireValue0(), [False, False, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=outid, parent_component=parent_component)
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self.add_component(obj_and3)
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self.out.connect(0, obj_and3.out)
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class XnorGateComponent(TwoInputOneBitCircuit):
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"""Class representing two input XNOR gate.
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```
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┌──────┐
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───►│ =1 │
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│ │O──►
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───►│ │
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└──────┘
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```
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Description of the __init__ method.
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Args:
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a (Wire): First input wire.
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b (Wire): Second input wire.
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prefix (str, optional): Prefix name of XNOR gate. Defaults to "".
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outid (int, optional): Index of output wire. Defaults to 0.
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parent_component (object, optional) Object of upper component of which XNOR gate is a subcomponent. Defaults to None.
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"""
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def __init__(self, a: Wire, b: Wire, prefix: str = "", outid: int = 0, parent_component: object = None):
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super().__init__(a, b, prefix=prefix, name=prefix)
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self.out = Bus(self.prefix+"_out", 1)
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self.disable_generation = True
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obj_and1 = Maji(a, b, ConstantWireValue1(), inverts=[True, True, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), parent_component = parent_component)
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self.add_component(obj_and1)
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obj_and2 = Maji(a, b, ConstantWireValue1(), inverts=[False, False, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), parent_component = parent_component)
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self.add_component(obj_and2)
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# sum
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obj_and3 = Maji(obj_and1.out, obj_and2.out, ConstantWireValue1(), [True, True, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=outid, parent_component=parent_component)
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self.add_component(obj_and3)
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self.out.connect(0, obj_and3.out)
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class HalfAdder(TwoInputOneBitCircuit):
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"""Class representing two input one bit half adder.
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```
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┌──────┐
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───►│ ├─► Sum
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│ │
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───►│ ├─► Cout
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└──────┘
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```
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Description of the __init__ method.
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Args:
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a (Wire, optional): First input wire. Defaults to Wire(name="a").
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b (Wire, optional): Second input wire. Defaults to Wire(name="b").
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prefix (str, optional): Prefix name of half adder. Defaults to "".
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name (str, optional): Name of half adder. Defaults to "ha".
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"""
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use_verilog_instance = False
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def __init__(self, a: Wire = Wire(name="a"), b: Wire = Wire(name="b"), prefix: str = "", name: str = "ha"):
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super().__init__(a, b, prefix=prefix, name=name)
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# 2 wires for component's bus output (sum, cout)
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self.out = Bus(self.prefix+"_out", 2)
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|
||||
obj_or = OrGate (a, b, prefix=self.prefix+"_or" +str(self.get_instance_num(cls=OrGate)), outid=0, parent_component=self)
|
||||
self.add_component(obj_or)
|
||||
|
||||
# cout
|
||||
obj_and = AndGate(a, b, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), outid=1, parent_component=self)
|
||||
self.add_component(obj_and)
|
||||
self.out.connect(1, obj_and.out)
|
||||
|
||||
# sum
|
||||
obj_maji = Maji(obj_or.out, obj_and.out, ConstantWireValue0(), [False, True, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=0, parent_component=self)
|
||||
self.add_component(obj_maji)
|
||||
self.out.connect(0, obj_maji.out)
|
||||
|
||||
def get_sum_wire(self):
|
||||
"""Get output wire carrying sum value.
|
||||
|
||||
Returns:
|
||||
Wire: Return sum wire.
|
||||
"""
|
||||
return self.out.get_wire(0)
|
||||
|
||||
def get_carry_wire(self):
|
||||
"""Get output wire carrying carry out value.
|
||||
|
||||
Returns:
|
||||
Wire: Return carry out wire.
|
||||
"""
|
||||
return self.out.get_wire(1)
|
||||
|
||||
def get_init_v_flat(self):
|
||||
""" support of custom PDK """
|
||||
if not self.use_verilog_instance:
|
||||
return super().get_init_v_flat()
|
||||
|
||||
return " " + self.use_verilog_instance.format(
|
||||
**{
|
||||
"unit": self.prefix,
|
||||
"wirea": f"1'b{self.a.value}" if self.a.is_const() else self.a.name,
|
||||
"wireb": f"1'b{self.b.value}" if self.b.is_const() else self.b.name,
|
||||
"wireys": self.get_sum_wire().prefix,
|
||||
"wireyc": self.get_carry_wire().prefix,
|
||||
}) + ";\n"
|
||||
|
||||
def get_self_init_v_hier(self):
|
||||
""" support of custom PDK """
|
||||
if not self.use_verilog_instance:
|
||||
return super().get_self_init_v_hier()
|
||||
|
||||
unique_out_wires = []
|
||||
for o in self.out.bus:
|
||||
unique_out_wires.append(o.name+"_outid"+str(self.out.bus.index(o))) if o.is_const() or o.name in [self.a.name, self.b.name] else unique_out_wires.append(o.name)
|
||||
|
||||
return " " + self.use_verilog_instance.format(
|
||||
**{
|
||||
"unit": self.prefix,
|
||||
"wirea": self.a.name,
|
||||
"wireb": self.b.name,
|
||||
"wireys": unique_out_wires[0],
|
||||
"wireyc": unique_out_wires[1],
|
||||
}) + ";\n"
|
||||
|
||||
def get_circuit_v(self):
|
||||
""" support of custom PDK """
|
||||
if not self.use_verilog_instance:
|
||||
return super().get_circuit_v()
|
||||
|
||||
return f"{self.get_prototype_v_hier()}" + \
|
||||
f"{self.get_self_init_v_hier()}" + \
|
||||
f"endmodule"
|
||||
|
||||
|
||||
class partialAdder(TwoInputOneBitCircuit):
|
||||
"""Class representing two input one bit propagate/generate logic block.
|
||||
|
||||
```
|
||||
┌──────┐
|
||||
A ───►│ ├─► P
|
||||
B ───►│ ├─► G
|
||||
Cin ───►│ ├─► S
|
||||
└──────┘
|
||||
```
|
||||
|
||||
Description of the __init__ method.
|
||||
|
||||
Args:
|
||||
a (Wire, optional): First input wire. Defaults to Wire(name="a").
|
||||
b (Wire, optional): Second input wire. Defaults to Wire(name="b").
|
||||
prefix (str, optional): Prefix name of pg logic block. Defaults to "".
|
||||
name (str, optional): Name of pg logic block. Defaults to "pg_logic".
|
||||
"""
|
||||
def __init__(self, a: Wire = Wire(name="a"), b: Wire = Wire(name="b"), cin: Wire = Wire(name="cin"), prefix: str = "", name: str = "pg_logic"):
|
||||
super().__init__(a, b, prefix=prefix, name=name)
|
||||
# 3 wires for component's bus output (propagate, generate, sum)
|
||||
self.out = Bus(self.prefix+"_out", 3)
|
||||
|
||||
# PG logic
|
||||
propagate_or = OrGate (a, b, prefix=self.prefix+"_or" +str(self.get_instance_num(cls=OrGate)), outid=0, parent_component=self)
|
||||
self.add_component(propagate_or)
|
||||
|
||||
generate_and = AndGate(a, b, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), outid=1, parent_component=self)
|
||||
self.add_component(generate_and)
|
||||
|
||||
fa = FullAdder(self, a, b, cin, prefix=self.prefix+"_fa" +str(self.get_instance_num(cls=FullAdder)), parent_component=self)
|
||||
self.add_component(fa)
|
||||
|
||||
self.out.connect(0, propagate_or.out)
|
||||
self.out.connect(1, generate_and.out)
|
||||
self.out.connect(2, fa.get_sum_wire())
|
||||
|
||||
def get_propagate_wire(self):
|
||||
"""Get output wire carrying propagate signal value.
|
||||
|
||||
Returns:
|
||||
Wire: Return propagate wire.
|
||||
"""
|
||||
return self.out.get_wire(0)
|
||||
|
||||
def get_generate_wire(self):
|
||||
"""Get output wire carrying generate signal value.
|
||||
|
||||
Returns:
|
||||
Wire: Return generate wire.
|
||||
"""
|
||||
return self.out.get_wire(1)
|
||||
|
||||
def get_sum_wire(self):
|
||||
"""Get output wire carrying sum value.
|
||||
|
||||
Returns:
|
||||
Wire: Return sum wire.
|
||||
"""
|
||||
return self.out.get_wire(2)
|
||||
|
||||
|
||||
class HalfSubtractor(TwoInputOneBitCircuit):
|
||||
"""Class representing two input one bit half subtractor.
|
||||
|
||||
```
|
||||
┌──────┐
|
||||
───►│ ├─► Difference
|
||||
│ │
|
||||
───►│ ├─► Bout
|
||||
└──────┘
|
||||
```
|
||||
|
||||
Description of the __init__ method.
|
||||
|
||||
Args:
|
||||
a (Wire, optional): First input wire. Defaults to Wire(name="a").
|
||||
b (Wire, optional): Second input wire. Defaults to Wire(name="b").
|
||||
prefix (str, optional): Prefix name of half subtractor adder. Defaults to "".
|
||||
name (str, optional): Name of half subtractor adder. Defaults to "hs".
|
||||
"""
|
||||
def __init__(self, a: Wire = Wire(name="a"), b: Wire = Wire(name="b"), prefix: str = "", name: str = "hs"):
|
||||
super().__init__(a, b, prefix=prefix, name=name)
|
||||
# 2 wires for component's bus output (difference, bout)
|
||||
self.out = Bus(self.prefix+"_out", 2)
|
||||
|
||||
# Difference
|
||||
# XOR gate for calculation of 1-bit difference
|
||||
propagate_or = OrGate (a, b, prefix=self.prefix+"_or" +str(self.get_instance_num(cls=OrGate)), outid=0, parent_component=self)
|
||||
self.add_component(propagate_or)
|
||||
|
||||
generate_and = AndGate(a, b, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), outid=1, parent_component=self)
|
||||
self.add_component(generate_and)
|
||||
|
||||
difference_xor = Maji(propagate_or.out, generate_and.out, ConstantWireValue0(), [False, True, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=0, parent_component=self)
|
||||
self.add_component(difference_xor)
|
||||
self.out.connect(0, difference_xor.out.get_wire(0))
|
||||
|
||||
# Bout
|
||||
# NOT and AND gates for calculation of 1-bit borrow out
|
||||
not_obj = NotGate(a=self.a, prefix=self.prefix+"_not"+str(self.get_instance_num(cls=NotGate)), parent_component=self)
|
||||
self.add_component(not_obj)
|
||||
|
||||
borrow_and = AndGate(a=not_obj.out, b=self.b, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), outid=1, parent_component=self)
|
||||
self.add_component(borrow_and)
|
||||
self.out.connect(1, borrow_and.out)
|
||||
|
||||
def get_difference_wire(self):
|
||||
"""Get output wire carrying difference value.
|
||||
|
||||
Returns:
|
||||
Wire: Return difference wire.
|
||||
"""
|
||||
return self.out.get_wire(0)
|
||||
|
||||
def get_borrow_wire(self):
|
||||
"""Get output wire carrying borrow out value.
|
||||
|
||||
Returns:
|
||||
Wire: Return borrow out wire.
|
||||
"""
|
||||
return self.out.get_wire(1)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user