All Workflows generate.yml

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All actors lukasplevac

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All status success failure waiting running

Static write FA to PGAdder

generate.yml #28:Commit e662c52e75 pushed by lukasplevac

main

2025-01-19 18:12:34 +00:00

1m51s

Code generation fix

generate.yml #27:Commit 6c8c791fb5 pushed by lukasplevac

main

2025-01-19 17:37:08 +00:00

1m58s

unexpected keyword argument 'parent_component'

generate.yml #26:Commit db25df54cd pushed by lukasplevac

main

2025-01-15 18:35:02 +00:00

1m45s

Incorect FA instance create

generate.yml #25:Commit cf4a6ccc52 pushed by lukasplevac

main

2025-01-15 18:31:32 +00:00

16s

Full adder missing import

generate.yml #24:Commit aefc20693a pushed by lukasplevac

main

2025-01-15 18:28:49 +00:00

17s

Imprt missing full adder

generate.yml #23:Commit 395750eac5 pushed by lukasplevac

main

2025-01-15 18:24:08 +00:00

17s

GCP PGA ADDER

generate.yml #22:Commit d0501238f8 pushed by lukasplevac

main

2025-01-06 12:04:25 +00:00

27s

Update readme

generate.yml #21:Commit 8adba05ba4 pushed by lukasplevac

main

2024-11-16 19:56:53 +00:00

1m45s

Simple generate example

generate.yml #20:Commit db231dd7f7 pushed by lukasplevac

main

2024-11-16 19:49:17 +00:00

1m48s

Aktualizovat README.md

generate.yml #19:Commit e576a9fd81 pushed by lukasplevac

main

2024-11-14 14:49:58 +00:00

1m48s

Fix unsigned mul test

generate.yml #18:Commit bb94958118 pushed by lukasplevac

main

2024-11-14 14:24:54 +00:00

1m51s

Remove iverilog from pipe

generate.yml #17:Commit 5bb50a325f pushed by lukasplevac

main

2024-11-14 14:22:01 +00:00

1m35s

Fixing pipeline

generate.yml #16:Commit 975ab01a1c pushed by lukasplevac

main

2024-11-14 14:19:26 +00:00

18s

Fix mux with wrong gate ordering

generate.yml #15:Commit c476479827 pushed by lukasplevac

main

2024-11-14 14:19:06 +00:00

0s

Fix mux with wrong gate ordering

codeql-analysis.yml #14:Commit c476479827 pushed by lukasplevac

main

2024-11-14 14:17:10 +00:00

40s

All working muls and adders

codeql-analysis.yml #13:Scheduled

main

2024-11-08 04:44:53 +00:00

47s

All working muls and adders

codeql-analysis.yml #12:Scheduled

main

2024-11-01 04:44:48 +00:00

42s

All working muls and adders

codeql-analysis.yml #11:Scheduled

main

2024-10-25 04:48:01 +01:00

3m56s

All working muls and adders

codeql-analysis.yml #10:Scheduled

main

2024-10-19 09:39:58 +01:00

0s

All working muls and adders

generate.yml #9:Commit 4eb65e10da pushed by lukasplevac

main

2024-10-19 14:32:36 +01:00

26m57s

All working muls and adders

codeql-analysis.yml #8:Commit 4eb65e10da pushed by lukasplevac

main

2024-10-18 21:39:58 +01:00

0s

Fully working xorGateComponent

codeql-analysis.yml #7:Scheduled

main

2024-10-12 09:39:58 +01:00

0s

Fully working xorGateComponent

generate.yml #6:Commit 09a12f3df7 pushed by lukasplevac

main

2024-10-11 15:40:01 +01:00

3s

Fully working xorGateComponent

codeql-analysis.yml #5:Commit 09a12f3df7 pushed by lukasplevac

main

2024-10-11 15:39:58 +01:00

0s

Fixed RCA by test

generate.yml #4:Commit c61244c966 pushed by lukasplevac

main

2024-10-09 15:40:00 +01:00

2s

Fixed RCA by test

codeql-analysis.yml #3:Commit c61244c966 pushed by lukasplevac

main

2024-10-09 15:39:58 +01:00

0s

Added support for MIG excluded xor and xnor gate

generate.yml #2:Commit ad9f62e3de pushed by lukasplevac

main

2024-10-08 13:29:08 +01:00

3s

Added support for MIG excluded xor and xnor gate

codeql-analysis.yml #1:Commit ad9f62e3de pushed by lukasplevac

main

2024-10-08 13:29:04 +01:00

0s