dissertation_thesis/ariths-gen-mig
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Full adder missing import
Some checks failed
BUILD / test (push) Failing after 15s
Details

Browse Source
This commit is contained in:
Lukáš Plevač 2025-01-15 19:28:29 +01:00
parent 395750eac5
commit aefc20693a
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
ariths_gen/one_bit_circuits/one_bit_components/two_input_one_bit_components.py
View File

@ -1,4 +1,5 @@
from ariths_gen.core.one_bit_circuits import TwoInputOneBitCircuit, FullAdder
from ariths_gen.core.one_bit_circuits import TwoInputOneBitCircuit
from .three_input_one_bit_components import FullAdder
from ariths_gen.one_bit_circuits.logic_gates import AndGate, NandGate, OrGate, NorGate, NotGate
from ariths_gen.one_bit_circuits import Maji
from ariths_gen.wire_components import Wire, Bus