dissertation_thesis/ariths-gen-mig
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  • b66c1bdfe0 Import fix Honza 2022-01-06 06:42:26 +01:00
  • 9aa0fb1858 Added broken array multiplier and truncated multiplier implementations. Tried testing them, but seems buggy. Needs further work. Honza 2022-01-06 06:39:58 +01:00
  • f830029c54 Added truncated multiplier circuit implementation. Needs testing. Honza 2022-01-04 03:13:21 +01:00
  • c8ed08691f Updated functionality of the extend_bus method. Honza 2021-11-16 00:02:52 +01:00
  • 2083ed35a1 Returned inner circuit's input buses extension feature back to its original form. Honza 2021-11-15 22:58:34 +01:00
  • f582ee729e Updated generation of hierarchical circuits to allow proper naming consistency between the subcomponent modules and their corresponding invocations. honzastor 2021-10-25 01:11:34 +02:00
  • 5d41997560 Added assertion checks for the same input bus lengths when initializing arithmetic circuits. honzastor 2021-10-24 18:48:00 +02:00
  • 49cf3150ca
         Merge pull request #7 from ehw-fit/devel Vojta Mrazek 2021-10-11 08:02:52 +02:00
  • d41c5f3c94 Updated exportation of signed arithmetic circuits to python representation. Also unified some methods from arithmetic_circuit.py into general_circuit.py. honzastor 2021-10-10 22:15:13 +02:00
  • cfb5bba3ec Bitwise and operation fix. honzastor 2021-10-10 00:02:58 +02:00
  • 16c1757bc3 Added signedness support for the output C code representation. Also modified the testing scripts and the chr2c.py converter accordingly and did some documentation changes (even made a small change in readme.md). Signedness support for the output python representation is TBD. honzastor 2021-10-09 23:45:54 +02:00
  • 598c10e052 Merge branch 'main' of github.com:ehw-fit/ariths-gen Vojta Mrazek 2021-10-04 12:19:55 +02:00
  • 152a6b1583
         Python eval (#4) Vojta Mrazek 2021-10-04 11:58:28 +02:00
  • 995107eecc Removing of file closing Vojta Mrazek 2021-09-23 08:50:18 +02:00
  • bee2086705
         Devel (#2) Vojta Mrazek 2021-09-18 12:55:31 +02:00
  • eba0a7a938 Made some minor changes concerning proper exportation of multiplier circuits. honzastor 2021-09-09 13:57:36 +02:00
  • e16de78c2b Updated logic behind generating export representations, mainly focused around circuit and its buses and subcomponents namings. honzastor 2021-09-07 17:39:39 +02:00
  • bfc806081e Made some minor changes and updated creation of MAC circuit. honzastor 2021-09-07 17:35:41 +02:00
  • f1303864ca test all Vojta Mrazek 2021-09-07 09:44:23 +02:00
  • fffb928875 auto test MAC Vojta Mrazek 2021-09-07 08:32:52 +02:00
  • a1827c957c Modified definition of MAC class to allow proper generation of output representations. honzastor 2021-09-06 15:17:31 +02:00
  • 8c0f24cd2d General MAC circuit Vojta Mrazek 2021-09-06 12:52:13 +02:00
  • a4dca24fc2 CGP format minor Vojta Mrazek 2021-06-23 14:09:46 +02:00
  • 0a487ee699 CGP format Vojta Mrazek 2021-06-23 14:08:49 +02:00
  • 87a7f2b8bb pip in actions Vojta Mrazek 2021-06-23 13:46:25 +02:00
  • c6e542231c CGP tests; reversed output order Vojta Mrazek 2021-06-23 13:43:58 +02:00
  • 5228923b69 doc on main branch only Vojta Mrazek 2021-06-18 12:40:56 +02:00
  • cfe0ca6b4b
         Automated testing, preparing the package for publishing (#1) Vojta Mrazek 2021-06-18 12:38:11 +02:00
  • f1f487a126 Small fix honzastor 2021-05-05 18:30:21 +02:00
  • 0d98fc0a2f Adding generated program documentation and chr2c.py script. honzastor 2021-05-05 18:27:47 +02:00
  • 50c33d27d2 Updated generated circuits. honzastor 2021-04-28 21:47:33 +02:00
  • e5f2dd893a Fixed proper generated circuits names (mistakenly named cska as csa). honzastor 2021-04-28 21:39:58 +02:00
  • f6838e50bd
         Merge pull request #4 from honzastor/develop Jan Klhůfek 2021-04-24 00:04:31 +02:00
  • 4740371c06 Deleted presentation of previous generator state. honzastor 2021-04-24 00:00:48 +02:00
  • 0f66c5a2e9 Fixed proper connections in submodules instantiation in hierarchical Verilog generation. Sample generated circuits were also accordingly updated. honzastor 2021-04-23 11:49:24 +02:00
  • a17e38b2d1 Uploading C code circuit simulations. honzastor 2021-04-23 02:48:32 +02:00
  • 670ba45ee5 Generated sample circuits for various representations. Updated C code circuits testing simulations and did some cleanup. honzastor 2021-04-23 02:44:14 +02:00
  • f57a633f6c Renamed generated circuits folders. honzastor 2021-04-22 20:56:38 +02:00
  • 8f911560b0 Folder renaming test honzastor 2021-04-22 20:23:57 +02:00
  • ad1c6ec557 Updated circuits documentation. honzastor 2021-04-21 13:42:07 +02:00
  • 8e950fc51f Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits. honzastor 2021-04-21 11:33:07 +02:00
  • 068def0226 Added documentation of classes methods. honzastor 2021-04-06 01:39:11 +02:00
  • a328e91996 Removed automatic documentation generation from git action. honzastor 2021-03-31 04:43:35 +02:00
  • a336a683e7 Added some code documentation and updated git action to generate it. honzastor 2021-03-31 04:40:54 +02:00
  • 7a6d5213f8 Updating gitignore honzastor 2021-03-30 16:15:54 +02:00
  • 8807ebfb66 Merge branch 'develop' of https://github.com/honzastor/bc_arithmetic_circuits_generator into develop honzastor 2021-03-30 16:14:45 +02:00
  • 5fe150a824 Adding possibility for automatic generation using git actions. honzastor 2021-03-30 16:13:42 +02:00
  • 82d2d02ef5
         Delete ariths_gen/one_bit_circuits/logic_gates/__pycache__ directory Jan Klhůfek 2021-03-30 03:13:15 +02:00
  • debef13087
         Delete ariths_gen/one_bit_circuits/one_bit_components/__pycache__ directory Jan Klhůfek 2021-03-30 03:13:04 +02:00
  • 9a4c2c4dd7
         Delete ariths_gen/multi_bit_circuits/multipliers/__pycache__ directory Jan Klhůfek 2021-03-30 03:12:43 +02:00
  • d27fbf7088
         Delete ariths_gen/multi_bit_circuits/adders/__pycache__ directory Jan Klhůfek 2021-03-30 03:12:31 +02:00
  • 669920b0d5
         Delete ariths_gen/wire_components/__pycache__ directory Jan Klhůfek 2021-03-30 03:12:11 +02:00
  • 1e2ae53df5
         Delete ariths_gen/one_bit_circuits/__pycache__ directory Jan Klhůfek 2021-03-30 03:11:57 +02:00
  • e28574a7c9
         Delete ariths_gen/multi_bit_circuits/__pycache__ directory Jan Klhůfek 2021-03-30 03:11:38 +02:00
  • 87105eaaa6
         Delete ariths_gen/core/__pycache__ directory Jan Klhůfek 2021-03-30 03:11:13 +02:00
  • 86479086c0
         Delete ariths_gen/__pycache__ directory Jan Klhůfek 2021-03-30 03:11:03 +02:00
  • 4a9408401e Typo fix. honzastor 2021-03-30 03:06:41 +02:00
  • 69e2514852 Updated project's structure. Renamed class names to properly fit Python naming convention. TBD: proper documentation. honzastor 2021-03-30 03:04:48 +02:00
  • 27866a5513 Made some bugfixes concerning hierarchical generation and updated generated circuits. honzastor 2021-03-29 22:50:24 +02:00
  • f7620f98e4 Generated various circuits representations and updated testing of C circuits. honzastor 2021-03-28 20:16:45 +02:00
  • acd3d51a62 Updating some minor changes. honzastor 2021-03-28 18:17:10 +02:00
  • 6f02fa94d1
         Deleting docs folder for GIT consistency Jan Klhůfek 2021-03-23 16:13:51 +01:00
  • af8cd2c93b no actions Vojta Mrazek 2021-03-23 14:05:54 +01:00
  • ec09e606b9 Merge branch 'develop' of github.com:honzastor/bc_arithmetic_circuits_generator into develop Vojta Mrazek 2021-03-23 14:04:57 +01:00
  • 07a16a498c [create-pull-request] automated change github-actions[bot] 2021-03-23 12:50:43 +00:00
  • 9e99c98220
         Merge pull request #2 from honzastor/create-pull-request/patch Vojta Mrazek 2021-03-23 13:51:57 +01:00
  • 7ba6db3e54 [create-pull-request] automated change github-actions[bot] 2021-03-23 12:50:43 +00:00
  • ac2654b527
         Merge pull request #1 from mrazekv/develop Vojta Mrazek 2021-03-23 13:49:37 +01:00
  • a8a8779616 action2 Vojta Mrazek 2021-03-23 13:46:23 +01:00
  • 915f494331 workflow Vojta Mrazek 2021-03-23 13:41:56 +01:00
  • 5788b6a879 Pushing circuits generation example. honzastor 2021-03-22 10:49:54 +01:00
  • 8df8e72810 Test commit honzastor 2021-03-22 00:31:59 +01:00
  • 792d0c5db1 Did some code refactoring concerning one bit circuits generation. Added multiple one/multi bit circuits. TBD: Generate and test different circuits, implement divider circuits, comment code, add verification/optimization of Verilog/BLIF files using yosys tool. honzastor 2021-03-22 00:22:01 +01:00
  • d86ddcac09 Implemented unsigned dadda multiplier circuit. Updated generation of export formats. TBD: Proper testing, modification of dadda with cla adder, write shell script for Verilog and Blif equivalence check. honzastor 2021-03-15 01:08:47 +01:00
  • f76284fcaa Updated cgp chromosomes for 1 bit multipliers. honzastor 2021-03-04 19:34:08 +01:00
  • e8cffeca91 Generated and tested generated circuits. honzastor 2021-03-04 18:59:33 +01:00
  • f28069da5f Refactored code and made some small bugfixes for generating exports. honzastor 2021-03-04 18:57:32 +01:00
  • 3aa6ecc368 Merge branch 'develop' of https://github.com/honzastor/bc_arithmetic_circuits_generator into develop honzastor 2021-03-01 21:41:37 +01:00
  • 7a37a646c6 Pushing last updated file. honzastor 2021-03-01 21:38:04 +01:00
  • 2e80db21bc
         Delete logic_gates_generator.py Jan Klhůfek 2021-03-01 21:36:23 +01:00
  • e4722c662d Implemented multiplier circuits, verilog and cgp export generation and changed generator's structure. Prone to error! Needs proper testing. TBD honzastor 2021-03-01 21:32:29 +01:00
  • ef5dc80382 Implemented generation to flat Verilog format and improved some other minor bits of code. honzastor 2021-02-16 10:41:29 +01:00
  • c9ddb834f7 Generated flat Verilog adder and gate circuits. Minor update to C code logic gates. honzastor 2021-02-16 10:38:36 +01:00
  • 193d504120 Generated hierarchical C code circuits and updated testing script correspondigly. honzastor 2021-02-12 01:45:26 +01:00
  • 397d3bc658 Added generation of hierarchical C code for implemented circuits. honzastor 2021-02-12 01:43:44 +01:00
  • 94af6fec34 Also uploading previously presented presentation. honzastor 2021-02-09 21:03:34 +01:00
  • f1142b51d9 Implemented basic tests for generated flat C code circuits. honzastor 2021-02-09 21:02:50 +01:00
  • de127e8c46 Added signed rca circuit. honzastor 2021-02-09 20:53:53 +01:00
  • ee73047199 Edited example circuits generation. honzastor 2021-01-18 19:34:05 +01:00
  • 4f8de30911 Implementation organized into multiple scripts. Added basic generation example call. Adjusting code to PEP8 standard (except long lines).) honzastor 2021-01-18 19:29:31 +01:00
  • b7c896872e Made small bugfixes in C code generation. root 2020-12-28 15:11:22 +01:00
  • 2a4609234c Merge branch 'develop' of https://github.com/honzastor/bc_arithmetic_circuits_generator into develop root 2020-12-28 01:31:05 +01:00
  • 6fe6d2c3d6 Changed implementaion of generating C code from circuits. root 2020-12-28 01:30:52 +01:00
  • b3e0e9f48f
         Delete generator_test.py Jan Klhůfek 2020-12-28 01:29:53 +01:00
  • e15fa5aed5 Changed code generation to C language. root 2020-12-28 00:41:01 +01:00
  • 67a1dfa148 Updated C code generation wire names. root 2020-12-13 14:53:20 +01:00
  • 01f473e727 Added c code generation for logic gates, one bit adders, rca. root 2020-12-11 22:57:32 +01:00
  • f18f6159f5 Started work on exporting adders into .c files. Needs optimization. root 2020-12-11 03:48:04 +01:00
  • 7fba0f0aea Added ripple carry adder and started work on C code generation. root 2020-12-10 22:37:10 +01:00
  • 99d23be531 Implemented logic for wire, bus, logic gates, and 1-bit adders. root 2020-12-10 03:52:00 +01:00