Pushing last updated file.
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honzastor
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e4722c662d
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7a37a646c6
@ -1,235 +0,0 @@
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from wire_components import wire
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""" LOGIC GATE COMPONENTS """
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class logic_gate():
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def __init__(self, a: wire, b: wire, prefix: str = "gate"):
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self.a = wire(name=prefix+"_"+a.name.replace(prefix+"_", ""), value=a.value)
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self.b = wire(name=prefix+"_"+b.name.replace(prefix+"_", ""), value=b.value)
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self.prefix = prefix
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def get_component_types(self):
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return list([self])
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""" C CODE GENERATION """
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# FLAT C #
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@staticmethod
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def get_includes_c():
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return f"#include <stdio.h>\n#include <stdint.h>\n\n"
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def get_prototype_c(self):
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self.a.name = self.a.name.replace(self.prefix, "", 1)
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self.b.name = self.b.name.replace(self.prefix, "", 1)
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return f"uint8_t {self.prefix}_{self.gate_type}(uint8_t {self.a.name}, uint8_t {self.b.name})" + "{" + "\n"
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def get_function_c(self):
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return f"{self.a.get_wire_value_c()} {self.operator} {self.b.get_wire_value_c()}"
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def get_declaration_c_flat(self):
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return f"{self.a.get_declaration_c()}{self.b.get_declaration_c()}{self.output.get_declaration_c()}"
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def get_init_c_flat(self):
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return f"{self.a.name} {self.operator} {self.b.name}"
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# Generating flat C code representation of the logic gate itself
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# (i.e. not as a component of bigger circuit)
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def get_c_code(self, file_object):
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file_object.write(self.get_includes_c())
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file_object.write(self.get_prototype_c())
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file_object.write(" return "+(self.get_function_c())+";\n}")
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file_object.close()
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# HIERARCHICAL C GENERATION #
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def get_function_block_c(self):
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self.a.name = "a"
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self.b.name = "b"
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return f"{self.get_prototype_c()}" + \
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f" return "+(self.get_function_c())+";\n}\n\n"
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def get_invocation_c(self, a: wire, b: wire):
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return f"{self.gate_type}({a.name}, {b.name});"
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def get_gate_output_c(self, a: wire, b: wire, offset: int = 0):
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return f"({self.gate_type}({a.name}, {b.name}) & 0x01) << {offset}"
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""" VERILOG CODE GENERATION """
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# FLAT VERILOG #
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def get_prototype_v(self):
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self.a.name = self.a.name.replace(self.prefix, "", 1)
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self.b.name = self.b.name.replace(self.prefix, "", 1)
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self.output.name = self.output.name.replace(self.prefix, "", 1)
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return f"module {self.prefix}_{self.gate_type}(input {self.a.name}, input {self.b.name}, output {self.output.name});\n"
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def get_declaration_v_flat(self):
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return f"{self.a.get_declaration_v()}{self.b.get_declaration_v()}{self.output.get_declaration_v()}"
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def get_function_v(self):
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return f"{self.a.name} {self.operator} {self.b.name}"
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def get_init_v_flat(self):
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return f"{self.a.name} {self.operator} {self.b.name}"
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# Generating flat Verilog code representation of the logic gate itself
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# (i.e. not as a component of bigger circuit)
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def get_v_code(self, file_object):
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file_object.write(self.get_prototype_v())
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file_object.write(f" assign {self.output.name} = {self.get_function_v()};\n")
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file_object.write(f"endmodule")
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file_object.close()
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# Single-input
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class not_gate(logic_gate):
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def __init__(self, a: wire, prefix: str = "", outid: int = 0):
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self.gate_type = "not_gate"
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self.operator = "~"
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self.a = wire(name=prefix+"_"+a.name.replace(prefix+"_", ""), value=a.value)
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self.prefix = prefix
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if self.a.value == 1:
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self.output = wire(name=prefix+"_y"+str(outid), value=0)
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else:
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self.output = wire(name=prefix+"_y"+str(outid), value=1)
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""" C CODE GENERATION """
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# FLAT C #
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def get_prototype_c(self):
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self.a.name = self.a.name.replace(self.prefix, "", 1)
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return f"uint8_t {self.prefix}_{self.gate_type}(uint8_t {self.a.name})" + "{" + "\n"
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def get_function_c(self):
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return f"{self.operator}{self.a.get_wire_value_c()} & 0x01 << 0"
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def get_declaration_c(self):
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return f"{self.a.get_declaration_c()}{self.output.get_declaration_c()}"
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def get_init_c_flat(self):
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return f"{self.operator}{self.a.name}"
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# HIERARCHICAL C #
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def get_function_block_c(self):
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self.a.name = "a"
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return f"{self.get_prototype_c()}" + \
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f" return "+(self.get_function_c())+";\n}\n\n"
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def get_invocation_c(self, a: wire):
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return f"{self.gate_type}({a.name});"
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def get_gate_output_c(self, a: wire, offset: int = 0):
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return f"({self.gate_type}({a.name}) & 0x01) << {offset}"
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""" VERILOG CODE GENERATION """
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# FLAT VERILOG #
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def get_prototype_v(self):
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self.a.name = self.a.name.replace(self.prefix, "", 1)
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self.output.name = self.output.name.replace(self.prefix, "", 1)
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return f"module {self.prefix}_{self.gate_type}(input {self.a.name}, output {self.output.name});\n"
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def get_declaration_v_flat(self):
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return f"{self.a.get_declaration_v()}{self.output.get_declaration_v()}"
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def get_function_v(self):
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# self.a.name = self.a.name.replace(self.prefix+"_", "")
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return f" {self.operator}{self.a.name}"
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def get_init_v_flat(self):
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return f"{self.a.name} {self.operator} {self.b.name}"
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# Two-input
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class and_gate(logic_gate):
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def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
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super().__init__(a, b, prefix)
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self.gate_type = "and_gate"
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self.operator = "&"
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if a.value == 1 and b.value == 1:
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self.output = wire(name=prefix+"_y"+str(outid), value=1)
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else:
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self.output = wire(name=prefix+"_y"+str(outid), value=0)
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class nand_gate(logic_gate):
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def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
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super().__init__(a, b, prefix)
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self.gate_type = "nand_gate"
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self.operator = "&"
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if (self.a.value == 1 and self.b.value == 1):
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self.output = wire(name=prefix+"_y"+str(outid), value=0)
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else:
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self.output = wire(name=prefix+"_y"+str(outid), value=1)
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""" C CODE GENERATION """
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def get_function_c(self):
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return "~("+(super().get_function_c())+f") & 0x01 << 0"
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""" VERILOG CODE GENERATION """
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def get_function_v(self):
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return "~("+(super().get_function_v())+f")"
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class or_gate(logic_gate):
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def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
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super().__init__(a, b, prefix)
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self.gate_type = "or_gate"
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self.operator = "|"
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if self.a.value == 1 or self.b.value == 1:
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self.output = wire(name=prefix+"_y"+str(outid), value=1)
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else:
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self.output = wire(name=prefix+"_y"+str(outid), value=0)
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class nor_gate(logic_gate):
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def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
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super().__init__(a, b, prefix)
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self.gate_type = "nor_gate"
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self.operator = "|"
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if self.a.value == 1 or self.b.value == 1:
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self.output = wire(name=prefix+"_y"+str(outid), value=0)
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else:
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self.output = wire(name=prefix+"_y"+str(outid), value=1)
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""" C CODE GENERATION """
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def get_function_c(self):
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return "~("+(super().get_function_c())+") & 0x01 << 0"
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""" VERILOG CODE GENERATION """
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def get_function_v(self):
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return "~("+(super().get_function_v())+f")"
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class xor_gate(logic_gate):
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def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
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super().__init__(a, b, prefix)
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self.gate_type = "xor_gate"
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self.operator = "^"
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if (a.value == 1 and b.value == 0) or (a.value == 0 and b.value == 1):
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self.output = wire(name=prefix+"_y"+str(outid), value=1)
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else:
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self.output = wire(name=prefix+"_y"+str(outid), value=0)
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class xnor_gate(logic_gate):
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def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
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super().__init__(a, b, prefix)
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self.gate_type = "xnor_gate"
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self.operator = "^"
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if (self.a.value == 1 and self.b.value == 0) or (self.a.value == 0 and self.b.value == 1):
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self.output = wire(name=prefix+"_y"+str(outid), value=0)
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else:
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self.output = wire(name=prefix+"_y"+str(outid), value=1)
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""" C CODE GENERATION """
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def get_function_c(self):
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return "~("+(super().get_function_c())+") & 0x01 << 0"
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""" VERILOG CODE GENERATION """
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def get_function_v(self):
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return "~("+(super().get_function_v())+f")"
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@ -2,18 +2,21 @@
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class wire():
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def __init__(self, name: str = "w", value: int = 0, index: int = 0):
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def __init__(self, name: str, value: int = 0, index: int = 0):
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self.name = name
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self.prefix = name[0:int(name.rfind(str(index))-1)]
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if self.name.endswith("_"+str(index)):
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self.prefix = name[0:int(name.rfind(str(index))-1)]
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else:
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self.prefix = name
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self.value = value
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self.index = index
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# C CODE GENERATION #
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def get_declaration_c(self):
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return f" uint8_t {self.name} = 0;\n"
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return f" uint8_t {self.name} = {self.value};\n"
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def get_wire_value_c(self, offset: int = 0):
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name = self.name if self.prefix == "" else self.prefix
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def get_wire_value_c(self, offset: int = 0, prefix: str = ""):
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name = self.name if prefix == "" else prefix
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return f"(({name} >> {offset}) & 0x01)"
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def return_wire_value_c(self, offset: int = 0):
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@ -23,19 +26,22 @@ class wire():
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def get_declaration_v(self):
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return f" wire {self.name};\n"
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def get_wire_value_v(self, offset: int = 0, array: bool = False):
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name = self.name if self.prefix == "" else self.prefix
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def get_declaration_init_v(self):
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return f" wire {self.name} = {self.value};\n"
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def get_wire_value_v(self, offset: int = 0, prefix: str = "", array: bool = False):
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name = self.name if prefix == "" else prefix
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if array is True:
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return f"{name}[{offset}]"
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else:
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return f"{name}"
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def return_wire_value_v(self, offset: int = 0):
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def return_wire_value_v(self):
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return f"{self.name}"
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class bus():
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def __init__(self, prefix: str = "bus", N: int = 1):
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def __init__(self, prefix: str, N: int = 1):
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self.bus = [wire(name=prefix+"_"+str(i), index=i) for i in range(N)]
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self.prefix = prefix
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self.N = N
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@ -48,7 +54,7 @@ class bus():
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def connect(self, out_wire_index: int, inner_component_out_wire: wire):
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self.bus[out_wire_index] = inner_component_out_wire
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def get_wire(self, wire_index: int):
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def get_wire(self, wire_index: int = 0):
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return self.bus[wire_index]
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def bus_extend(self, N: int, prefix: str = "bus"):
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@ -56,14 +62,11 @@ class bus():
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self.N = N
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# C CODE GENERATION #
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def get_wire_value_c(self, offset: int = 0):
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return self.bus[offset].get_wire_value_c(offset=offset)
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def return_wire_value_c(self, offset: int = 0):
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self.bus[offset].return_wire_value_c(offset)
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def get_wire_value_c(self, offset: int = 0, prefix: str = ""):
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return self.get_wire(wire_index=offset).get_wire_value_c(offset=offset, prefix=prefix)
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def get_wire_declaration_c(self):
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return [w.get_declaration_c() for w in self.bus]
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return "".join([w.get_declaration_c() for w in self.bus])
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def get_declaration_c(self):
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if self.N > 8:
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@ -71,6 +74,12 @@ class bus():
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else:
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return f" uint8_t {self.prefix} = 0;\n"
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def return_wire_value_c(self, offset: int = 0):
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self.get_wire(wire_index=offset).return_wire_value_c(offset=offset)
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# VERILOG CODE GENERATION #
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def get_wire_value_v(self, offset: int = 0, array: bool = False):
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return self.bus[offset].get_wire_value_v(offset=offset, array=array)
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def get_wire_value_v(self, offset: int = 0, prefix: str = "", array: bool = False):
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return self.get_wire(wire_index=offset).get_wire_value_v(offset=offset, prefix=prefix, array=array)
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def get_wire_declaration_v(self):
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return "".join([w.get_declaration_v() for w in self.bus])
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