Added c code generation for logic gates, one bit adders, rca.
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@ -2,22 +2,34 @@
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#todo ??
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class wire():
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def __init__(self, index):
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self.index = index
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self.value = 0
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def __init__(self, value=0):
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#todo nechat inicializaci?
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self.value = value
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self.id=None
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def add_wire_id(self, wire_id):
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self.id = wire_id
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def get_wire_id(self):
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return self.id
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class bus():
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#inicializace sbernice
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def __init__(self, N=1):
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self.bus = [wire(index=i) for i in range(N)]
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self.bus = [wire() for i in range(N)]
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self.N = N
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#vraci drat na prislusnem indexu sbernice
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def get(self, wire_index):
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def get_wire(self, wire_index):
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return self.bus[wire_index]
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def add_wire_id(self, wire_id, wire_index=0):
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self.bus[wire_index].id = wire_id
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def get_wire_id(self, wire_index):
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return self.bus[wire_index].id
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#vraci logickou hodnotu vedenou na drate s prislusnym indexem
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def get_value(self, wire_index):
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def get_wire_value(self, wire_index):
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return self.bus[wire_index].value
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#pripojeni vstupni, vystupni hodnoty komponenty k sbernici
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@ -25,308 +37,389 @@ class bus():
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self.bus[wire_index].value = component_output_value
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#KOMPONENTY HRADEL
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#jednovstupove
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class not_gate():
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def __init__(self, input_a):
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self.gate_type = "not_gate"
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if input_a == 1:
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self.y = 0
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else:
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self.y = 1
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class logic_gate():
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def export_to_C(self, filename, main_component=True, file_object=None, wire_id=0, line_var_cnt=0, init_run=True):
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with open(filename,'w') as f:
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if main_component == True:
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if main_component == True:
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with open(filename,'w') as f:
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f.write('#include <stdint.h>\n\n')
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f.write('uint8_t not_gate(uint8_t a) {\n')
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f.write(' uint8_t y;\n')
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f.write(' uint8_t n1 = (a >> 0) & 0x1;\n')
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f.write(' y = ~n1;\n')
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if self.gate_type == 'not_gate':
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f.write('uint8_t not_gate(uint8_t a) {\n')
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f.write(' uint8_t y = 0;\n')
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f.write(' uint8_t n1 = (a >> 0) & 0x1;\n')
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f.write(' y |= (~n1 & 0x01) << 0;\n')
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elif self.gate_type == 'and_gate':
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f.write('uint8_t and_gate(uint8_t a, uint8_t b) {\n')
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f.write(' uint8_t y = 0;\n')
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f.write(' uint8_t n1 = (a >> 0) & 0x1;\n')
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f.write(' uint8_t n2 = (b >> 0) & 0x1;\n')
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f.write(' y |= ((n1 & n2) & 0x01) << 0;\n')
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elif self.gate_type == 'or_gate':
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f.write('uint8_t or_gate(uint8_t a, uint8_t b) {\n')
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f.write(' uint8_t y = 0;\n')
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f.write(' uint8_t n1 = (a >> 0) & 0x1;\n')
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f.write(' uint8_t n2 = (b >> 0) & 0x1;\n')
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f.write(' y |= ((n1 | n2) & 0x01) << 0;\n')
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elif self.gate_type == 'xor_gate':
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f.write('uint8_t xor_gate(uint8_t a, uint8_t b) {\n')
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f.write(' uint8_t y = 0;\n')
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f.write(' uint8_t n1 = (a >> 0) & 0x1;\n')
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f.write(' uint8_t n2 = (b >> 0) & 0x1;\n')
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f.write(' y |= ((n1 ^ n2) & 0x01) << 0;\n')
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f.write(' return y;\n')
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f.write('}\n')
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else:
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if init_run == True:
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if line_var_cnt != 0:
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file_object.write(', ')
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file_object.write(f'n_{wire_id}=0')
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else:
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if init_run == True:
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if line_var_cnt == 0:
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file_object.write(' uint8_t ')
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else:
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pass
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file_object.write(', ')
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file_object.write(f'n_{wire_id}=0')
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self.y.add_wire_id(wire_id)
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else:
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if self.gate_type == 'not_gate':
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file_object.write(f' n_{self.y.get_wire_id()} = ~n_{self.input.get_wire_id(0)};\n')
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else:
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file_object.write(f' n_{self.y.get_wire_id()} = n_{self.input.get_wire_id(0)} {self.operator} n_{self.input.get_wire_id(1)};\n')
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#jednovstupove
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class not_gate(logic_gate):
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def __init__(self, input_wire_a):
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self.gate_type = 'not_gate'
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self.wires_N = 2
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self.input = bus(1)
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self.input.bus[0] = input_wire_a
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if input_wire_a.value == 1:
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self.y = wire(0)
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else:
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self.y = wire(1)
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#dvouvstupove
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class or_gate():
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def __init__(self, input_a, input_b):
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self.gate_type = "or_gate"
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if (input_a == 1 or input_b == 1):
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self.y = 1
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class and_gate(logic_gate):
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def __init__(self, input_wire_a, input_wire_b):
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self.gate_type = 'and_gate'
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self.wires_N = 3
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self.operator = '&'
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self.input = bus(2)
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self.input.bus[0] = input_wire_a
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self.input.bus[1] = input_wire_b
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if input_wire_a.value == 1 and input_wire_b.value == 1:
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self.y = wire(1)
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else:
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self.y = 0
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self.y = wire(0)
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def export_to_C(self, filename, main_component=True, file_object=None, wire_id=0, line_var_cnt=0, init_run=True):
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with open(filename,'w') as f:
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if main_component == True:
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f.write('#include <stdint.h>\n\n')
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f.write('uint8_t or_gate(uint8_t a, uint8_t b) {\n')
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f.write(' uint8_t y;\n')
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f.write(' uint8_t n1 = (a >> 0) & 0x1;\n')
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f.write(' uint8_t n2 = (b >> 0) & 0x1;\n')
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f.write(' y = n1 | n2;\n')
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f.write(' return y;\n')
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f.write('}\n')
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else:
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#todo wtf
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if init_run == True:
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if line_var_cnt != 0:
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file_object.write(', ')
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file_object.write(f'n_{wire_id}=0')
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else:
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pass
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class xor_gate():
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def __init__(self, input_a, input_b):
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self.gate_type = "xor_gate"
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if (input_a == 1 and input_b == 0) or (input_a == 0 and input_b == 1):
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self.y = 1
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class or_gate(logic_gate):
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def __init__(self, input_wire_a, input_wire_b):
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self.gate_type = 'or_gate'
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self.wires_N = 3
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self.operator = '|'
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self.input = bus(2)
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self.input.bus[0] = input_wire_a
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self.input.bus[1] = input_wire_b
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if input_wire_a.value == 1 or input_wire_b.value == 1:
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self.y = wire(1)
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else:
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self.y = 0
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self.y = wire(0)
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def export_to_C(self, filename, main_component=True, file_object=None, wire_id=0, line_var_cnt=0, init_run=True):
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with open(filename,'w') as f:
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if main_component == True:
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f.write('#include <stdint.h>\n\n')
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f.write('uint8_t xor_gate(uint8_t a, uint8_t b) {\n')
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f.write(' uint8_t y;\n')
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f.write(' uint8_t n1 = (a >> 0) & 0x1;\n')
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f.write(' uint8_t n2 = (b >> 0) & 0x1;\n')
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f.write(' y = n1 ^ n2;\n')
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f.write(' return y;\n')
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f.write('}\n')
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else:
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if init_run == True:
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if line_var_cnt != 0:
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file_object.write(', ')
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file_object.write(f'n_{wire_id}=0')
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else:
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pass
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class and_gate():
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def __init__(self, input_a, input_b):
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self.gate_type = "and_gate"
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if input_a == 1 and input_b == 1:
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self.y = 1
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class xor_gate(logic_gate):
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def __init__(self, input_wire_a, input_wire_b):
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self.gate_type = 'xor_gate'
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self.wires_N = 3
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self.operator = '^'
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self.input = bus(2)
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self.input.bus[0] = input_wire_a
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self.input.bus[1] = input_wire_b
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if (input_wire_a.value == 1 and input_wire_b.value == 0) or (input_wire_a.value == 0 and input_wire_b.value == 1):
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self.y = wire(1)
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else:
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self.y = 0
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def export_to_C(self, filename, main_component=True, file_object=None, wire_id=0, line_var_cnt=0, init_run=True):
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with open(filename,'w') as f:
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if main_component == True:
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f.write('#include <stdint.h>\n\n')
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f.write('uint8_t and_gate(uint8_t a, uint8_t b) {\n')
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f.write(' uint8_t y;\n')
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f.write(' uint8_t n1 = (a >> 0) & 0x1;\n')
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f.write(' uint8_t n2 = (b >> 0) & 0x1;\n')
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f.write(' y = n1 & n2;\n')
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f.write(' return y;\n')
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f.write('}\n')
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else:
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if init_run == True:
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if line_var_cnt != 0:
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file_object.write(', ')
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file_object.write(f'n_{wire_id}=0')
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else:
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pass
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self.y = wire(0)
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#ARITMETICKE OBVODY
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class arithmetic_circuit():
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def __init__(self):
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self.component_list = []
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self.input_N = 0
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self.carry_out_gate = None
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self.sum_out_gates = []
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def add_component(self, component):
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self.component_list.append(component)
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def get_component_index(self, component):
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return self.component_list.index(component)
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def get_previous_component(self):
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return self.component_list[-1]
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#zpravidla posledni bit ve vystupnim vektoru bitu
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def get_carry_out(self):
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return self.out.get(-1).value
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#pomocna funkce
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def wire_index_offset(self, index):
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return index
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def get_carry_out_wire(self):
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return self.carry_out_gate.y
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#todo jinak zpravidla posledni bit ve vystupnim vektoru bitu
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def get_carry_out_val(self):
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return self.carry_out_gate.value
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def get_sum_out(self, index):
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#todo
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def get_sum_out_val(self, index):
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return self.out.get_value(index)
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#Export do jinych reprezentaci
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def export_to_C(self, filename, main_component=True, file_object=None, wire_id=0, line_var_cnt=0, init_run=True):
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self.line_wires_cnt = 0
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if main_component == True:
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with open(filename,'w') as f:
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f.write('#include <stdint.h>\n\n')
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#DEKLARACE FUNKCE PRO DANY TYP OBVODU
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##
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if self.circuit_type == 'ha':
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f.write('uint8_t ha(uint8_t a, uint8_t b) {\n')
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f.write(' uint8_t out = 0;\n')
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elif self.circuit_type == 'fa':
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f.write('uint8_t fa(uint8_t a, uint8_t b, uint8_t cin) {\n')
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f.write(' uint8_t out = 0;\n')
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else:
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f.write(f'uint64_t {self.circuit_type}(uint64_t a, uint64_t b) ')
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f.write('{\n')
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elif self.circuit_type == 'rca_'+str(int(self.input_N/2)):
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f.write('uint64_t rca(uint64_t a, uint64_t b) {\n')
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f.write(' uint64_t out = 0;\n')
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f.write('uint8_t ')
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for component in self.component_list:
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component.export_to_C(filename, False)
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#DEKLARACE DRATU
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##
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#deklarace vstupu obvodu
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for in_wire_index in range(self.input_N):
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if line_var_cnt == 0:
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f.write(' uint8_t ')
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else:
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f.write(', ')
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f.write(f'n_{in_wire_index}=0')
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self.inputs.add_wire_id(wire_id, in_wire_index)
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line_var_cnt += 1
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wire_id += 1
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#deklarace vstupu a vystupu hradel vnitrni logiky obvodu
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if self.circuit_type != 'ha' and self.circuit_type != 'fa':
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for component in self.component_list:
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if component.circuit_type == 'ha':
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component.export_to_C(filename, False, file_object=f, wire_id=wire_id, line_var_cnt=line_var_cnt)
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wire_id += 2
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line_var_cnt += 2
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elif component.circuit_type == 'fa':
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component.export_to_C(filename, False, file_object=f, wire_id=wire_id, line_var_cnt=line_var_cnt)
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wire_id += 5
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line_var_cnt += 5
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else:
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for component in self.component_list:
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#zapis 8 promennych na radek, odradkovani pro prehlednost
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if line_var_cnt >= 8:
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f.write(';\n')
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line_var_cnt = 0
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component.export_to_C(filename, False, file_object=f, wire_id=wire_id, line_var_cnt=line_var_cnt)
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wire_id += 1
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line_var_cnt += 1
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f.write(';\n')
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#PRIRAZENI VSTUPNICH HODNOT K DRATUM
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if self.circuit_type == 'fa':
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f.write(f' n_{self.inputs.get_wire_id(0)} = (a >> 0) & 0x1;\n')
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f.write(f' n_{self.inputs.get_wire_id(1)} = (b >> 0) & 0x1;\n')
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f.write(f' n_{self.inputs.get_wire_id(2)} = (cin >> 0) & 0x1;\n')
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else:
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for in_wire_index in range(0, int(self.input_N/2)):
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f.write(f' n_{self.inputs.get_wire_id(in_wire_index)} = (a >> {in_wire_index}) & 0x1;\n')
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for in_wire_index in range(0, int(self.input_N/2)):
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f.write(f' n_{self.inputs.get_wire_id(in_wire_index + int(self.input_N/2))} = (b >> {in_wire_index}) & 0x1;\n')
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#VYPOCTY VYSTUPNICH HODNOT HRADEL
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##
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for component in self.component_list:
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component.export_to_C(filename, False, file_object=f, init_run=False)
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#PRIRAZENI VYSTUPU
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##
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for out_wire_index in range(self.out.N):
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if self.circuit_type != 'ha' and self.circuit_type != 'fa':
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if out_wire_index == (self.out.N)-1:
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out_component_index = self.component_list[out_wire_index-1].get_component_index(self.carry_out_gate)
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component = self.component_list[out_wire_index-1]
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else:
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out_component_index = self.component_list[out_wire_index].get_component_index(self.sum_out_gates[out_wire_index])
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component = self.component_list[out_wire_index]
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if component.circuit_type == 'ha':
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out_component_index = out_component_index * out_wire_index
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elif component.circuit_type == 'fa':
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if out_wire_index == (self.out.N)-1:
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out_component_index += 5 * (out_wire_index-2) + 2
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else:
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out_component_index += 5 * (out_wire_index-1) + 2
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wire_id = self.wire_index_offset(out_component_index+self.input_N)
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f.write(f' out |= (n_{wire_id} & 0x01) << {out_wire_index};\n')
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else:
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#Cout
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if out_wire_index == (self.out.N)-1:
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out_component_index = self.get_component_index(self.carry_out_gate)
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#Sum
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else:
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out_component_index = self.get_component_index(self.sum_out_gates[out_wire_index])
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wire_id = self.wire_index_offset(out_component_index+self.input_N)
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f.write(f' out |= (n_{wire_id} & 0x01) << {out_wire_index};\n')
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f.write(' return out;\n')
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f.write('}\n')
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else:
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if init_run == True:
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for component in self.component_list:
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#zapis 8 promennych na radek, odradkovani pro prehlednost
|
||||
if line_var_cnt >= 8:
|
||||
file_object.write(';\n')
|
||||
line_var_cnt = 0
|
||||
|
||||
component.export_to_C(filename, False, file_object=file_object, wire_id=wire_id, line_var_cnt=line_var_cnt)
|
||||
wire_id += 1
|
||||
line_var_cnt += 1
|
||||
else:
|
||||
for component in self.component_list:
|
||||
component.export_to_C(filename, False, file_object=file_object, init_run=False)
|
||||
|
||||
|
||||
|
||||
class half_adder(arithmetic_circuit):
|
||||
def __init__(self, input_a, input_b):
|
||||
def __init__(self, input_wire_a, input_wire_b):
|
||||
super().__init__()
|
||||
self.circuit_type = "ha"
|
||||
self.input_N = 2
|
||||
self.circuit_type = 'ha'
|
||||
self.inputs = bus(self.input_N)
|
||||
self.inputs.bus[0] = input_wire_a
|
||||
self.inputs.bus[1] = input_wire_b
|
||||
|
||||
#2 draty pro vystupy komponenty (sum, cout)
|
||||
self.out = bus(2)
|
||||
|
||||
#Sum
|
||||
#XOR hradlo pro vypocet jednobitového souctu (sum)
|
||||
obj_xor_gate = xor_gate(input_a, input_b)
|
||||
obj_xor_gate = xor_gate(input_wire_a, input_wire_b)
|
||||
self.add_component(obj_xor_gate)
|
||||
self.out.connect(0,obj_xor_gate.y)
|
||||
self.sum_out_gates.append(obj_xor_gate)
|
||||
|
||||
#Cout
|
||||
#AND hradlo pro vypocet jednobitoveho priznaku prenosu do vyssiho radu (cout)jednobitového souctu (sum)
|
||||
obj_and_gate = and_gate(input_a, input_b)
|
||||
obj_and_gate = and_gate(input_wire_a, input_wire_b)
|
||||
self.add_component(obj_and_gate)
|
||||
self.out.connect(1,obj_and_gate.y)
|
||||
|
||||
def get_sum_out(self):
|
||||
return self.out.get(0).value
|
||||
self.carry_out_gate = obj_and_gate
|
||||
|
||||
def export_to_C(self, filename, main_component=True, file_object=None, wire_id=0, line_var_cnt=0, init_run=True):
|
||||
if main_component == True:
|
||||
with open(filename,'w') as f:
|
||||
f.write('#include <stdint.h>\n\n')
|
||||
f.write('uint8_t ha(uint8_t a, uint8_t b) {\n')
|
||||
f.write(' uint8_t out = 0;\n')
|
||||
f.write(' uint8_t ')
|
||||
def get_sum_out_component(self):
|
||||
return self.component_list[0]
|
||||
|
||||
#inicializace vstupu
|
||||
for component in self.component_list:
|
||||
component.export_to_C(filename, False, file_object=f, wire_id=wire_id, line_var_cnt=line_var_cnt)
|
||||
wire_id +=1
|
||||
line_var_cnt +=1
|
||||
|
||||
if line_var_cnt == 8:
|
||||
line_var_cnt = 0
|
||||
f.write(';\n')
|
||||
|
||||
wire_id=0
|
||||
|
||||
#prirazeni hodnot
|
||||
for component in self.component_list:
|
||||
component.export_to_C(filename, False, file_object=f, wire_id=wire_id, init_run=False)
|
||||
wire_id +=1
|
||||
|
||||
|
||||
f.write(';\n')
|
||||
|
||||
f.write(' return out;\n')
|
||||
f.write('}\n')
|
||||
else:
|
||||
pass
|
||||
|
||||
def get_sum_out_wire(self):
|
||||
return self.out.get_wire(0)
|
||||
|
||||
|
||||
class full_adder(arithmetic_circuit):
|
||||
def __init__(self, input_a, input_b, carry_in):
|
||||
def __init__(self, input_wire_a, input_wire_b, carry_in_wire):
|
||||
super().__init__()
|
||||
self.circuit_type = "fa"
|
||||
self.input_N = 3
|
||||
self.circuit_type = 'fa'
|
||||
self.inputs = bus(self.input_N)
|
||||
self.inputs.bus[0] = input_wire_a
|
||||
self.inputs.bus[1] = input_wire_b
|
||||
self.inputs.bus[2] = carry_in_wire
|
||||
|
||||
|
||||
#2 draty pro vystupy komponenty (sum, cout)
|
||||
self.out = bus(2)
|
||||
|
||||
#PG logika
|
||||
propagate_xor_gate1 = xor_gate(input_a, input_b)
|
||||
propagate_xor_gate1 = xor_gate(input_wire_a, input_wire_b)
|
||||
self.add_component(propagate_xor_gate1)
|
||||
generate_and_gate1 = and_gate(input_a, input_b)
|
||||
generate_and_gate1 = and_gate(input_wire_a, input_wire_b)
|
||||
self.add_component(generate_and_gate1)
|
||||
|
||||
#Sum
|
||||
#XOR hradlo pro vypocet jednobitového souctu (sum)
|
||||
obj_xor_gate2 = xor_gate(propagate_xor_gate1.y, carry_in)
|
||||
obj_xor_gate2 = xor_gate(propagate_xor_gate1.y, carry_in_wire)
|
||||
self.add_component(obj_xor_gate2)
|
||||
self.out.connect(0,obj_xor_gate2.y)
|
||||
self.sum_out_gates.append(obj_xor_gate2)
|
||||
|
||||
#Cout
|
||||
#AND hradlo pro vypocet jednobitoveho priznaku prenosu do vyssiho radu (cout)jednobitového souctu (sum)
|
||||
obj_and_gate2 = and_gate(propagate_xor_gate1.y, carry_in)
|
||||
obj_and_gate2 = and_gate(propagate_xor_gate1.y, carry_in_wire)
|
||||
self.add_component(obj_and_gate2)
|
||||
|
||||
obj_or_gate = or_gate(generate_and_gate1.y, obj_and_gate2.y)
|
||||
self.add_component(obj_or_gate)
|
||||
|
||||
self.out.connect(1,obj_or_gate.y)
|
||||
self.carry_out_gate = obj_or_gate
|
||||
|
||||
#todo nechat?
|
||||
self.propagate = propagate_xor_gate1.y
|
||||
self.generate = generate_and_gate1.y
|
||||
|
||||
def get_sum_out(self):
|
||||
return self.out.get(0).value
|
||||
|
||||
def export_to_C(self, filename, main_component=True, file_object=None, wire_id=0, line_var_cnt=0, mode):
|
||||
if main_component == True:
|
||||
with open(filename,'w') as f:
|
||||
f.write('#include <stdint.h>\n\n')
|
||||
f.write('uint8_t fa(uint8_t a, uint8_t b, uint8_t cin) {\n')
|
||||
f.write(' uint8_t out = 0;\n')
|
||||
f.write(' uint8_t ')
|
||||
|
||||
for component in self.component_list:
|
||||
component.export_to_C(filename, False, file_object=f, wire_id=wire_id, line_var_cnt=line_var_cnt)
|
||||
wire_id +=1
|
||||
line_var_cnt +=1
|
||||
|
||||
if line_var_cnt == 8:
|
||||
f.write(';\n')
|
||||
|
||||
def get_sum_out_component(self):
|
||||
return self.component_list[0]
|
||||
|
||||
def get_sum_out_wire(self):
|
||||
return self.out.get_wire(0)
|
||||
|
||||
f.write(';\n')
|
||||
|
||||
f.write(' return out;\n')
|
||||
f.write('}\n')
|
||||
else:
|
||||
pass
|
||||
|
||||
|
||||
class ripple_carry_adder(arithmetic_circuit):
|
||||
def __init__(self, input_bus_a, input_bus_b):
|
||||
super().__init__()
|
||||
#todo zeptat se
|
||||
N = max(input_bus_a.N,input_bus_b.N)
|
||||
self.circuit_type = "rca_"+str(N)
|
||||
self.input_N = N * 2
|
||||
self.circuit_type = 'rca_'+str(N)
|
||||
self.sum_out_gates= []
|
||||
|
||||
self.inputs = bus(self.input_N)
|
||||
for i in range(N):
|
||||
self.inputs.bus[i] = input_bus_a.get_wire(i)
|
||||
for i in range(N):
|
||||
self.inputs.bus[i+N] = input_bus_b.get_wire(i)
|
||||
|
||||
#vystupni draty pro N souctu a vystupni priznak prenosu do vyssiho radu (cout)
|
||||
self.out = bus(N+1)
|
||||
|
||||
#postupne pridani jednobitovych scitacek
|
||||
for input_index in range(N):
|
||||
#prvni je polovicni scitacka
|
||||
if input_index == 0:
|
||||
obj_ha = half_adder(input_bus_a.get_value(input_index), input_bus_b.get_value(input_index))
|
||||
obj_ha = half_adder(input_bus_a.get_wire(input_index), input_bus_b.get_wire(input_index))
|
||||
self.add_component(obj_ha)
|
||||
self.out.connect(input_index, obj_ha.get_sum_out())
|
||||
self.out.connect(input_index, obj_ha)
|
||||
self.sum_out_gates.append(obj_ha.sum_out_gates[0])
|
||||
else:
|
||||
obj_fa = full_adder(input_bus_a.get_value(input_index), input_bus_b.get_value(input_index), self.get_previous_component().get_carry_out())
|
||||
obj_fa = full_adder(input_bus_a.get_wire(input_index), input_bus_b.get_wire(input_index), self.get_previous_component().get_carry_out_wire())
|
||||
self.add_component(obj_fa)
|
||||
self.out.connect(input_index, obj_fa.get_sum_out())
|
||||
self.out.connect(input_index, obj_fa.get_sum_out_wire())
|
||||
|
||||
self.sum_out_gates.append(obj_fa.sum_out_gates[0])
|
||||
if input_index == (N-1):
|
||||
self.out.connect(N, obj_fa.get_carry_out())
|
||||
|
||||
#Export do jinych reprezentaci
|
||||
#todo
|
||||
|
||||
self.out.connect(N, obj_fa.get_carry_out_wire())
|
||||
self.carry_out_gate = obj_fa.carry_out_gate
|
||||
Loading…
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Reference in New Issue
Block a user