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Generated flat Verilog adder and gate circuits. Minor update to C code logic gates.

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This commit is contained in:
honzastor 2021-02-16 10:38:36 +01:00
parent 193d504120
commit c9ddb834f7
22 changed files with 640 additions and 21 deletions
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6
Tests/C_circuits/Logic_gates/and_gate.c
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#include <stdio.h>
#include <stdint.h>
uint8_t and_gate(uint8_t a, uint8_t b){
return ((a >> 0) & 0x01) & ((b >> 0) & 0x01);
uint8_t _and_gate(uint8_t _a, uint8_t _b){
return ((_a >> 0) & 0x01) & ((_b >> 0) & 0x01);
}
#include <assert.h>
int main(){
for (int i = 0; i < 2; i++){
for (int j = 0; j < 2; j++){
assert((i & j) == and_gate(i,j));
assert((i & j) == _and_gate(i,j));
}
}
return 0;

6
Tests/C_circuits/Logic_gates/nand_gate.c
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#include <stdio.h>
#include <stdint.h>
uint8_t nand_gate(uint8_t a, uint8_t b){
return ~(((a >> 0) & 0x01) & ((b >> 0) & 0x01)) & 0x01 << 0;
uint8_t _nand_gate(uint8_t _a, uint8_t _b){
return ~(((_a >> 0) & 0x01) & ((_b >> 0) & 0x01)) & 0x01 << 0;
}
#include <assert.h>
int main(){
for (int i = 0; i < 2; i++){
for (int j = 0; j < 2; j++){
assert(!(i & j) == nand_gate(i,j));
assert(!(i & j) == _nand_gate(i,j));
}
}
return 0;

6
Tests/C_circuits/Logic_gates/nor_gate.c
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#include <stdio.h>
#include <stdint.h>
uint8_t nor_gate(uint8_t a, uint8_t b){
return ~(((a >> 0) & 0x01) | ((b >> 0) & 0x01)) & 0x01 << 0;
uint8_t _nor_gate(uint8_t _a, uint8_t _b){
return ~(((_a >> 0) & 0x01) | ((_b >> 0) & 0x01)) & 0x01 << 0;
}
#include <assert.h>
int main(){
for (int i = 0; i < 2; i++){
for (int j = 0; j < 2; j++){
assert(!(i | j) == nor_gate(i,j));
assert(!(i | j) == _nor_gate(i,j));
}
}
return 0;

6
Tests/C_circuits/Logic_gates/not_gate.c
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#include <stdio.h>
#include <stdint.h>
uint8_t not_gate(uint8_t a){
return ~((a >> 0) & 0x01) & 0x01 << 0;
uint8_t _not_gate(uint8_t _a){
return ~((_a >> 0) & 0x01) & 0x01 << 0;
}
#include <assert.h>
int main(){
for (int i = 0; i < 2; i++){
assert(!(i) == not_gate(i));
assert(!(i) == _not_gate(i));
}
return 0;
}

6
Tests/C_circuits/Logic_gates/or_gate.c
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@ -1,15 +1,15 @@
#include <stdio.h>
#include <stdint.h>
uint8_t or_gate(uint8_t a, uint8_t b){
return ((a >> 0) & 0x01) | ((b >> 0) & 0x01);
uint8_t _or_gate(uint8_t _a, uint8_t _b){
return ((_a >> 0) & 0x01) | ((_b >> 0) & 0x01);
}
#include <assert.h>
int main(){
for (int i = 0; i < 2; i++){
for (int j = 0; j < 2; j++){
assert((i | j) == or_gate(i,j));
assert((i | j) == _or_gate(i,j));
}
}
return 0;

6
Tests/C_circuits/Logic_gates/xnor_gate.c
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#include <stdio.h>
#include <stdint.h>
uint8_t xnor_gate(uint8_t a, uint8_t b){
return ~(((a >> 0) & 0x01) ^ ((b >> 0) & 0x01)) & 0x01 << 0;
uint8_t _xnor_gate(uint8_t _a, uint8_t _b){
return ~(((_a >> 0) & 0x01) ^ ((_b >> 0) & 0x01)) & 0x01 << 0;
}
#include <assert.h>
int main(){
for (int i = 0; i < 2; i++){
for (int j = 0; j < 2; j++){
assert(!(i ^ j) == xnor_gate(i,j));
assert(!(i ^ j) == _xnor_gate(i,j));
}
}
return 0;

6
Tests/C_circuits/Logic_gates/xor_gate.c
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@ -1,15 +1,15 @@
#include <stdio.h>
#include <stdint.h>
uint8_t xor_gate(uint8_t a, uint8_t b){
return ((a >> 0) & 0x01) ^ ((b >> 0) & 0x01);
uint8_t _xor_gate(uint8_t _a, uint8_t _b){
return ((_a >> 0) & 0x01) ^ ((_b >> 0) & 0x01);
}
#include <assert.h>
int main(){
for (int i = 0; i < 2; i++){
for (int j = 0; j < 2; j++){
assert((i ^ j) == xor_gate(i,j));
assert((i ^ j) == _xor_gate(i,j));
}
}
return 0;

22
Tests/Verilog_circuits/Flat_circuits/Adders/f_fa.v Normal file
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module f_fa(input a, input b, input cout, output [1:0]out);
wire f_fa_a;
wire f_fa_b;
wire f_fa_y0;
wire f_fa_y1;
wire f_fa_cout;
wire f_fa_y2;
wire f_fa_y3;
wire f_fa_y4;
assign f_fa_a = a;
assign f_fa_b = b;
assign f_fa_cout = cout;
assign f_fa_y0 = f_fa_a ^ f_fa_b;
assign f_fa_y1 = f_fa_a & f_fa_b;
assign f_fa_y2 = f_fa_y0 ^ f_fa_cout;
assign f_fa_y3 = f_fa_y0 & f_fa_cout;
assign f_fa_y4 = f_fa_y1 | f_fa_y3;
assign out[0] = f_fa_y2;
assign out[1] = f_fa_y4;
endmodule

14
Tests/Verilog_circuits/Flat_circuits/Adders/f_ha.v Normal file
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module f_ha(input a, input b, output [1:0]out);
wire f_ha_a;
wire f_ha_b;
wire f_ha_y0;
wire f_ha_y1;
assign f_ha_a = a;
assign f_ha_b = b;
assign f_ha_y0 = f_ha_a ^ f_ha_b;
assign f_ha_y1 = f_ha_a & f_ha_b;
assign out[0] = f_ha_y0;
assign out[1] = f_ha_y1;
endmodule

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Tests/Verilog_circuits/Flat_circuits/Adders/f_s_rca2.v Normal file
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module s_rca2(input [1:0] a, input [1:0] b, output [2:0] out);
wire s_rca2_ha_a_0;
wire s_rca2_ha_b_0;
wire s_rca2_ha_y0;
wire s_rca2_ha_y1;
wire s_rca2_fa1_a_1;
wire s_rca2_fa1_b_1;
wire s_rca2_fa1_y0;
wire s_rca2_fa1_y1;
wire s_rca2_fa1_s_rca2_ha_y1;
wire s_rca2_fa1_y2;
wire s_rca2_fa1_y3;
wire s_rca2_fa1_y4;
wire s_rca2_xor_1_a_1;
wire s_rca2_xor_1_b_1;
wire s_rca2_xor_1_y0;
wire s_rca2_xor_2_s_rca2_xor_1_y0;
wire s_rca2_xor_2_s_rca2_fa1_y4;
wire s_rca2_xor_2_y0;
assign s_rca2_ha_a_0 = a[0];
assign s_rca2_ha_b_0 = b[0];
assign s_rca2_ha_y0 = s_rca2_ha_a_0 ^ s_rca2_ha_b_0;
assign s_rca2_ha_y1 = s_rca2_ha_a_0 & s_rca2_ha_b_0;
assign s_rca2_fa1_a_1 = a[1];
assign s_rca2_fa1_b_1 = b[1];
assign s_rca2_fa1_s_rca2_ha_y1 = s_rca2_ha_y1[1];
assign s_rca2_fa1_y0 = s_rca2_fa1_a_1 ^ s_rca2_fa1_b_1;
assign s_rca2_fa1_y1 = s_rca2_fa1_a_1 & s_rca2_fa1_b_1;
assign s_rca2_fa1_y2 = s_rca2_fa1_y0 ^ s_rca2_fa1_s_rca2_ha_y1;
assign s_rca2_fa1_y3 = s_rca2_fa1_y0 & s_rca2_fa1_s_rca2_ha_y1;
assign s_rca2_fa1_y4 = s_rca2_fa1_y1 | s_rca2_fa1_y3;
assign s_rca2_xor_1_a_1 = a[1];
assign s_rca2_xor_1_b_1 = b[1];
assign s_rca2_xor_1_y0 = s_rca2_xor_1_a_1 ^ s_rca2_xor_1_b_1;
assign s_rca2_xor_2_s_rca2_xor_1_y0 = s_rca2_xor_1_y0;
assign s_rca2_xor_2_s_rca2_fa1_y4 = s_rca2_fa1_y4;
assign s_rca2_xor_2_y0 = s_rca2_xor_2_s_rca2_xor_1_y0 ^ s_rca2_xor_2_s_rca2_fa1_y4;
assign out[0] = s_rca2_ha_y0;
assign out[1] = s_rca2_fa1_y2;
assign out[2] = s_rca2_xor_2_y0;
endmodule

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Tests/Verilog_circuits/Flat_circuits/Adders/f_s_rca6.v Normal file
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module s_rca6(input [5:0] a, input [5:0] b, output [6:0] out);
wire s_rca6_ha_a_0;
wire s_rca6_ha_b_0;
wire s_rca6_ha_y0;
wire s_rca6_ha_y1;
wire s_rca6_fa1_a_1;
wire s_rca6_fa1_b_1;
wire s_rca6_fa1_y0;
wire s_rca6_fa1_y1;
wire s_rca6_fa1_s_rca6_ha_y1;
wire s_rca6_fa1_y2;
wire s_rca6_fa1_y3;
wire s_rca6_fa1_y4;
wire s_rca6_fa2_a_2;
wire s_rca6_fa2_b_2;
wire s_rca6_fa2_y0;
wire s_rca6_fa2_y1;
wire s_rca6_fa2_s_rca6_fa1_y4;
wire s_rca6_fa2_y2;
wire s_rca6_fa2_y3;
wire s_rca6_fa2_y4;
wire s_rca6_fa3_a_3;
wire s_rca6_fa3_b_3;
wire s_rca6_fa3_y0;
wire s_rca6_fa3_y1;
wire s_rca6_fa3_s_rca6_fa2_y4;
wire s_rca6_fa3_y2;
wire s_rca6_fa3_y3;
wire s_rca6_fa3_y4;
wire s_rca6_fa4_a_4;
wire s_rca6_fa4_b_4;
wire s_rca6_fa4_y0;
wire s_rca6_fa4_y1;
wire s_rca6_fa4_s_rca6_fa3_y4;
wire s_rca6_fa4_y2;
wire s_rca6_fa4_y3;
wire s_rca6_fa4_y4;
wire s_rca6_fa5_a_5;
wire s_rca6_fa5_b_5;
wire s_rca6_fa5_y0;
wire s_rca6_fa5_y1;
wire s_rca6_fa5_s_rca6_fa4_y4;
wire s_rca6_fa5_y2;
wire s_rca6_fa5_y3;
wire s_rca6_fa5_y4;
wire s_rca6_xor_1_a_5;
wire s_rca6_xor_1_b_5;
wire s_rca6_xor_1_y0;
wire s_rca6_xor_2_s_rca6_xor_1_y0;
wire s_rca6_xor_2_s_rca6_fa5_y4;
wire s_rca6_xor_2_y0;
assign s_rca6_ha_a_0 = a[0];
assign s_rca6_ha_b_0 = b[0];
assign s_rca6_ha_y0 = s_rca6_ha_a_0 ^ s_rca6_ha_b_0;
assign s_rca6_ha_y1 = s_rca6_ha_a_0 & s_rca6_ha_b_0;
assign s_rca6_fa1_a_1 = a[1];
assign s_rca6_fa1_b_1 = b[1];
assign s_rca6_fa1_s_rca6_ha_y1 = s_rca6_ha_y1[1];
assign s_rca6_fa1_y0 = s_rca6_fa1_a_1 ^ s_rca6_fa1_b_1;
assign s_rca6_fa1_y1 = s_rca6_fa1_a_1 & s_rca6_fa1_b_1;
assign s_rca6_fa1_y2 = s_rca6_fa1_y0 ^ s_rca6_fa1_s_rca6_ha_y1;
assign s_rca6_fa1_y3 = s_rca6_fa1_y0 & s_rca6_fa1_s_rca6_ha_y1;
assign s_rca6_fa1_y4 = s_rca6_fa1_y1 | s_rca6_fa1_y3;
assign s_rca6_fa2_a_2 = a[2];
assign s_rca6_fa2_b_2 = b[2];
assign s_rca6_fa2_s_rca6_fa1_y4 = s_rca6_fa1_y4[2];
assign s_rca6_fa2_y0 = s_rca6_fa2_a_2 ^ s_rca6_fa2_b_2;
assign s_rca6_fa2_y1 = s_rca6_fa2_a_2 & s_rca6_fa2_b_2;
assign s_rca6_fa2_y2 = s_rca6_fa2_y0 ^ s_rca6_fa2_s_rca6_fa1_y4;
assign s_rca6_fa2_y3 = s_rca6_fa2_y0 & s_rca6_fa2_s_rca6_fa1_y4;
assign s_rca6_fa2_y4 = s_rca6_fa2_y1 | s_rca6_fa2_y3;
assign s_rca6_fa3_a_3 = a[3];
assign s_rca6_fa3_b_3 = b[3];
assign s_rca6_fa3_s_rca6_fa2_y4 = s_rca6_fa2_y4[3];
assign s_rca6_fa3_y0 = s_rca6_fa3_a_3 ^ s_rca6_fa3_b_3;
assign s_rca6_fa3_y1 = s_rca6_fa3_a_3 & s_rca6_fa3_b_3;
assign s_rca6_fa3_y2 = s_rca6_fa3_y0 ^ s_rca6_fa3_s_rca6_fa2_y4;
assign s_rca6_fa3_y3 = s_rca6_fa3_y0 & s_rca6_fa3_s_rca6_fa2_y4;
assign s_rca6_fa3_y4 = s_rca6_fa3_y1 | s_rca6_fa3_y3;
assign s_rca6_fa4_a_4 = a[4];
assign s_rca6_fa4_b_4 = b[4];
assign s_rca6_fa4_s_rca6_fa3_y4 = s_rca6_fa3_y4[4];
assign s_rca6_fa4_y0 = s_rca6_fa4_a_4 ^ s_rca6_fa4_b_4;
assign s_rca6_fa4_y1 = s_rca6_fa4_a_4 & s_rca6_fa4_b_4;
assign s_rca6_fa4_y2 = s_rca6_fa4_y0 ^ s_rca6_fa4_s_rca6_fa3_y4;
assign s_rca6_fa4_y3 = s_rca6_fa4_y0 & s_rca6_fa4_s_rca6_fa3_y4;
assign s_rca6_fa4_y4 = s_rca6_fa4_y1 | s_rca6_fa4_y3;
assign s_rca6_fa5_a_5 = a[5];
assign s_rca6_fa5_b_5 = b[5];
assign s_rca6_fa5_s_rca6_fa4_y4 = s_rca6_fa4_y4[5];
assign s_rca6_fa5_y0 = s_rca6_fa5_a_5 ^ s_rca6_fa5_b_5;
assign s_rca6_fa5_y1 = s_rca6_fa5_a_5 & s_rca6_fa5_b_5;
assign s_rca6_fa5_y2 = s_rca6_fa5_y0 ^ s_rca6_fa5_s_rca6_fa4_y4;
assign s_rca6_fa5_y3 = s_rca6_fa5_y0 & s_rca6_fa5_s_rca6_fa4_y4;
assign s_rca6_fa5_y4 = s_rca6_fa5_y1 | s_rca6_fa5_y3;
assign s_rca6_xor_1_a_5 = a[5];
assign s_rca6_xor_1_b_5 = b[5];
assign s_rca6_xor_1_y0 = s_rca6_xor_1_a_5 ^ s_rca6_xor_1_b_5;
assign s_rca6_xor_2_s_rca6_xor_1_y0 = s_rca6_xor_1_y0;
assign s_rca6_xor_2_s_rca6_fa5_y4 = s_rca6_fa5_y4;
assign s_rca6_xor_2_y0 = s_rca6_xor_2_s_rca6_xor_1_y0 ^ s_rca6_xor_2_s_rca6_fa5_y4;
assign out[0] = s_rca6_ha_y0;
assign out[1] = s_rca6_fa1_y2;
assign out[2] = s_rca6_fa2_y2;
assign out[3] = s_rca6_fa3_y2;
assign out[4] = s_rca6_fa4_y2;
assign out[5] = s_rca6_fa5_y2;
assign out[6] = s_rca6_xor_2_y0;
endmodule

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Tests/Verilog_circuits/Flat_circuits/Adders/f_s_rca8.v Normal file
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module s_rca8(input [7:0] a, input [7:0] b, output [8:0] out);
wire s_rca8_ha_a_0;
wire s_rca8_ha_b_0;
wire s_rca8_ha_y0;
wire s_rca8_ha_y1;
wire s_rca8_fa1_a_1;
wire s_rca8_fa1_b_1;
wire s_rca8_fa1_y0;
wire s_rca8_fa1_y1;
wire s_rca8_fa1_s_rca8_ha_y1;
wire s_rca8_fa1_y2;
wire s_rca8_fa1_y3;
wire s_rca8_fa1_y4;
wire s_rca8_fa2_a_2;
wire s_rca8_fa2_b_2;
wire s_rca8_fa2_y0;
wire s_rca8_fa2_y1;
wire s_rca8_fa2_s_rca8_fa1_y4;
wire s_rca8_fa2_y2;
wire s_rca8_fa2_y3;
wire s_rca8_fa2_y4;
wire s_rca8_fa3_a_3;
wire s_rca8_fa3_b_3;
wire s_rca8_fa3_y0;
wire s_rca8_fa3_y1;
wire s_rca8_fa3_s_rca8_fa2_y4;
wire s_rca8_fa3_y2;
wire s_rca8_fa3_y3;
wire s_rca8_fa3_y4;
wire s_rca8_fa4_a_4;
wire s_rca8_fa4_b_4;
wire s_rca8_fa4_y0;
wire s_rca8_fa4_y1;
wire s_rca8_fa4_s_rca8_fa3_y4;
wire s_rca8_fa4_y2;
wire s_rca8_fa4_y3;
wire s_rca8_fa4_y4;
wire s_rca8_fa5_a_5;
wire s_rca8_fa5_b_5;
wire s_rca8_fa5_y0;
wire s_rca8_fa5_y1;
wire s_rca8_fa5_s_rca8_fa4_y4;
wire s_rca8_fa5_y2;
wire s_rca8_fa5_y3;
wire s_rca8_fa5_y4;
wire s_rca8_fa6_a_6;
wire s_rca8_fa6_b_6;
wire s_rca8_fa6_y0;
wire s_rca8_fa6_y1;
wire s_rca8_fa6_s_rca8_fa5_y4;
wire s_rca8_fa6_y2;
wire s_rca8_fa6_y3;
wire s_rca8_fa6_y4;
wire s_rca8_fa7_a_7;
wire s_rca8_fa7_b_7;
wire s_rca8_fa7_y0;
wire s_rca8_fa7_y1;
wire s_rca8_fa7_s_rca8_fa6_y4;
wire s_rca8_fa7_y2;
wire s_rca8_fa7_y3;
wire s_rca8_fa7_y4;
wire s_rca8_xor_1_a_7;
wire s_rca8_xor_1_b_7;
wire s_rca8_xor_1_y0;
wire s_rca8_xor_2_s_rca8_xor_1_y0;
wire s_rca8_xor_2_s_rca8_fa7_y4;
wire s_rca8_xor_2_y0;
assign s_rca8_ha_a_0 = a[0];
assign s_rca8_ha_b_0 = b[0];
assign s_rca8_ha_y0 = s_rca8_ha_a_0 ^ s_rca8_ha_b_0;
assign s_rca8_ha_y1 = s_rca8_ha_a_0 & s_rca8_ha_b_0;
assign s_rca8_fa1_a_1 = a[1];
assign s_rca8_fa1_b_1 = b[1];
assign s_rca8_fa1_s_rca8_ha_y1 = s_rca8_ha_y1[1];
assign s_rca8_fa1_y0 = s_rca8_fa1_a_1 ^ s_rca8_fa1_b_1;
assign s_rca8_fa1_y1 = s_rca8_fa1_a_1 & s_rca8_fa1_b_1;
assign s_rca8_fa1_y2 = s_rca8_fa1_y0 ^ s_rca8_fa1_s_rca8_ha_y1;
assign s_rca8_fa1_y3 = s_rca8_fa1_y0 & s_rca8_fa1_s_rca8_ha_y1;
assign s_rca8_fa1_y4 = s_rca8_fa1_y1 | s_rca8_fa1_y3;
assign s_rca8_fa2_a_2 = a[2];
assign s_rca8_fa2_b_2 = b[2];
assign s_rca8_fa2_s_rca8_fa1_y4 = s_rca8_fa1_y4[2];
assign s_rca8_fa2_y0 = s_rca8_fa2_a_2 ^ s_rca8_fa2_b_2;
assign s_rca8_fa2_y1 = s_rca8_fa2_a_2 & s_rca8_fa2_b_2;
assign s_rca8_fa2_y2 = s_rca8_fa2_y0 ^ s_rca8_fa2_s_rca8_fa1_y4;
assign s_rca8_fa2_y3 = s_rca8_fa2_y0 & s_rca8_fa2_s_rca8_fa1_y4;
assign s_rca8_fa2_y4 = s_rca8_fa2_y1 | s_rca8_fa2_y3;
assign s_rca8_fa3_a_3 = a[3];
assign s_rca8_fa3_b_3 = b[3];
assign s_rca8_fa3_s_rca8_fa2_y4 = s_rca8_fa2_y4[3];
assign s_rca8_fa3_y0 = s_rca8_fa3_a_3 ^ s_rca8_fa3_b_3;
assign s_rca8_fa3_y1 = s_rca8_fa3_a_3 & s_rca8_fa3_b_3;
assign s_rca8_fa3_y2 = s_rca8_fa3_y0 ^ s_rca8_fa3_s_rca8_fa2_y4;
assign s_rca8_fa3_y3 = s_rca8_fa3_y0 & s_rca8_fa3_s_rca8_fa2_y4;
assign s_rca8_fa3_y4 = s_rca8_fa3_y1 | s_rca8_fa3_y3;
assign s_rca8_fa4_a_4 = a[4];
assign s_rca8_fa4_b_4 = b[4];
assign s_rca8_fa4_s_rca8_fa3_y4 = s_rca8_fa3_y4[4];
assign s_rca8_fa4_y0 = s_rca8_fa4_a_4 ^ s_rca8_fa4_b_4;
assign s_rca8_fa4_y1 = s_rca8_fa4_a_4 & s_rca8_fa4_b_4;
assign s_rca8_fa4_y2 = s_rca8_fa4_y0 ^ s_rca8_fa4_s_rca8_fa3_y4;
assign s_rca8_fa4_y3 = s_rca8_fa4_y0 & s_rca8_fa4_s_rca8_fa3_y4;
assign s_rca8_fa4_y4 = s_rca8_fa4_y1 | s_rca8_fa4_y3;
assign s_rca8_fa5_a_5 = a[5];
assign s_rca8_fa5_b_5 = b[5];
assign s_rca8_fa5_s_rca8_fa4_y4 = s_rca8_fa4_y4[5];
assign s_rca8_fa5_y0 = s_rca8_fa5_a_5 ^ s_rca8_fa5_b_5;
assign s_rca8_fa5_y1 = s_rca8_fa5_a_5 & s_rca8_fa5_b_5;
assign s_rca8_fa5_y2 = s_rca8_fa5_y0 ^ s_rca8_fa5_s_rca8_fa4_y4;
assign s_rca8_fa5_y3 = s_rca8_fa5_y0 & s_rca8_fa5_s_rca8_fa4_y4;
assign s_rca8_fa5_y4 = s_rca8_fa5_y1 | s_rca8_fa5_y3;
assign s_rca8_fa6_a_6 = a[6];
assign s_rca8_fa6_b_6 = b[6];
assign s_rca8_fa6_s_rca8_fa5_y4 = s_rca8_fa5_y4[6];
assign s_rca8_fa6_y0 = s_rca8_fa6_a_6 ^ s_rca8_fa6_b_6;
assign s_rca8_fa6_y1 = s_rca8_fa6_a_6 & s_rca8_fa6_b_6;
assign s_rca8_fa6_y2 = s_rca8_fa6_y0 ^ s_rca8_fa6_s_rca8_fa5_y4;
assign s_rca8_fa6_y3 = s_rca8_fa6_y0 & s_rca8_fa6_s_rca8_fa5_y4;
assign s_rca8_fa6_y4 = s_rca8_fa6_y1 | s_rca8_fa6_y3;
assign s_rca8_fa7_a_7 = a[7];
assign s_rca8_fa7_b_7 = b[7];
assign s_rca8_fa7_s_rca8_fa6_y4 = s_rca8_fa6_y4[7];
assign s_rca8_fa7_y0 = s_rca8_fa7_a_7 ^ s_rca8_fa7_b_7;
assign s_rca8_fa7_y1 = s_rca8_fa7_a_7 & s_rca8_fa7_b_7;
assign s_rca8_fa7_y2 = s_rca8_fa7_y0 ^ s_rca8_fa7_s_rca8_fa6_y4;
assign s_rca8_fa7_y3 = s_rca8_fa7_y0 & s_rca8_fa7_s_rca8_fa6_y4;
assign s_rca8_fa7_y4 = s_rca8_fa7_y1 | s_rca8_fa7_y3;
assign s_rca8_xor_1_a_7 = a[7];
assign s_rca8_xor_1_b_7 = b[7];
assign s_rca8_xor_1_y0 = s_rca8_xor_1_a_7 ^ s_rca8_xor_1_b_7;
assign s_rca8_xor_2_s_rca8_xor_1_y0 = s_rca8_xor_1_y0;
assign s_rca8_xor_2_s_rca8_fa7_y4 = s_rca8_fa7_y4;
assign s_rca8_xor_2_y0 = s_rca8_xor_2_s_rca8_xor_1_y0 ^ s_rca8_xor_2_s_rca8_fa7_y4;
assign out[0] = s_rca8_ha_y0;
assign out[1] = s_rca8_fa1_y2;
assign out[2] = s_rca8_fa2_y2;
assign out[3] = s_rca8_fa3_y2;
assign out[4] = s_rca8_fa4_y2;
assign out[5] = s_rca8_fa5_y2;
assign out[6] = s_rca8_fa6_y2;
assign out[7] = s_rca8_fa7_y2;
assign out[8] = s_rca8_xor_2_y0;
endmodule

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module u_rca3(input [2:0] a, input [2:0] b, output [3:0] out);
wire u_rca3_ha_a_0;
wire u_rca3_ha_b_0;
wire u_rca3_ha_y0;
wire u_rca3_ha_y1;
wire u_rca3_fa1_a_1;
wire u_rca3_fa1_b_1;
wire u_rca3_fa1_y0;
wire u_rca3_fa1_y1;
wire u_rca3_fa1_u_rca3_ha_y1;
wire u_rca3_fa1_y2;
wire u_rca3_fa1_y3;
wire u_rca3_fa1_y4;
wire u_rca3_fa2_a_2;
wire u_rca3_fa2_b_2;
wire u_rca3_fa2_y0;
wire u_rca3_fa2_y1;
wire u_rca3_fa2_u_rca3_fa1_y4;
wire u_rca3_fa2_y2;
wire u_rca3_fa2_y3;
wire u_rca3_fa2_y4;
assign u_rca3_ha_a_0 = a[0];
assign u_rca3_ha_b_0 = b[0];
assign u_rca3_ha_y0 = u_rca3_ha_a_0 ^ u_rca3_ha_b_0;
assign u_rca3_ha_y1 = u_rca3_ha_a_0 & u_rca3_ha_b_0;
assign u_rca3_fa1_a_1 = a[1];
assign u_rca3_fa1_b_1 = b[1];
assign u_rca3_fa1_u_rca3_ha_y1 = u_rca3_ha_y1[1];
assign u_rca3_fa1_y0 = u_rca3_fa1_a_1 ^ u_rca3_fa1_b_1;
assign u_rca3_fa1_y1 = u_rca3_fa1_a_1 & u_rca3_fa1_b_1;
assign u_rca3_fa1_y2 = u_rca3_fa1_y0 ^ u_rca3_fa1_u_rca3_ha_y1;
assign u_rca3_fa1_y3 = u_rca3_fa1_y0 & u_rca3_fa1_u_rca3_ha_y1;
assign u_rca3_fa1_y4 = u_rca3_fa1_y1 | u_rca3_fa1_y3;
assign u_rca3_fa2_a_2 = a[2];
assign u_rca3_fa2_b_2 = b[2];
assign u_rca3_fa2_u_rca3_fa1_y4 = u_rca3_fa1_y4[2];
assign u_rca3_fa2_y0 = u_rca3_fa2_a_2 ^ u_rca3_fa2_b_2;
assign u_rca3_fa2_y1 = u_rca3_fa2_a_2 & u_rca3_fa2_b_2;
assign u_rca3_fa2_y2 = u_rca3_fa2_y0 ^ u_rca3_fa2_u_rca3_fa1_y4;
assign u_rca3_fa2_y3 = u_rca3_fa2_y0 & u_rca3_fa2_u_rca3_fa1_y4;
assign u_rca3_fa2_y4 = u_rca3_fa2_y1 | u_rca3_fa2_y3;
assign out[0] = u_rca3_ha_y0;
assign out[1] = u_rca3_fa1_y2;
assign out[2] = u_rca3_fa2_y2;
assign out[3] = u_rca3_fa2_y4;
endmodule

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module u_rca5(input [4:0] a, input [4:0] b, output [5:0] out);
wire u_rca5_ha_a_0;
wire u_rca5_ha_b_0;
wire u_rca5_ha_y0;
wire u_rca5_ha_y1;
wire u_rca5_fa1_a_1;
wire u_rca5_fa1_b_1;
wire u_rca5_fa1_y0;
wire u_rca5_fa1_y1;
wire u_rca5_fa1_u_rca5_ha_y1;
wire u_rca5_fa1_y2;
wire u_rca5_fa1_y3;
wire u_rca5_fa1_y4;
wire u_rca5_fa2_a_2;
wire u_rca5_fa2_b_2;
wire u_rca5_fa2_y0;
wire u_rca5_fa2_y1;
wire u_rca5_fa2_u_rca5_fa1_y4;
wire u_rca5_fa2_y2;
wire u_rca5_fa2_y3;
wire u_rca5_fa2_y4;
wire u_rca5_fa3_a_3;
wire u_rca5_fa3_b_3;
wire u_rca5_fa3_y0;
wire u_rca5_fa3_y1;
wire u_rca5_fa3_u_rca5_fa2_y4;
wire u_rca5_fa3_y2;
wire u_rca5_fa3_y3;
wire u_rca5_fa3_y4;
wire u_rca5_fa4_a_4;
wire u_rca5_fa4_b_4;
wire u_rca5_fa4_y0;
wire u_rca5_fa4_y1;
wire u_rca5_fa4_u_rca5_fa3_y4;
wire u_rca5_fa4_y2;
wire u_rca5_fa4_y3;
wire u_rca5_fa4_y4;
assign u_rca5_ha_a_0 = a[0];
assign u_rca5_ha_b_0 = b[0];
assign u_rca5_ha_y0 = u_rca5_ha_a_0 ^ u_rca5_ha_b_0;
assign u_rca5_ha_y1 = u_rca5_ha_a_0 & u_rca5_ha_b_0;
assign u_rca5_fa1_a_1 = a[1];
assign u_rca5_fa1_b_1 = b[1];
assign u_rca5_fa1_u_rca5_ha_y1 = u_rca5_ha_y1[1];
assign u_rca5_fa1_y0 = u_rca5_fa1_a_1 ^ u_rca5_fa1_b_1;
assign u_rca5_fa1_y1 = u_rca5_fa1_a_1 & u_rca5_fa1_b_1;
assign u_rca5_fa1_y2 = u_rca5_fa1_y0 ^ u_rca5_fa1_u_rca5_ha_y1;
assign u_rca5_fa1_y3 = u_rca5_fa1_y0 & u_rca5_fa1_u_rca5_ha_y1;
assign u_rca5_fa1_y4 = u_rca5_fa1_y1 | u_rca5_fa1_y3;
assign u_rca5_fa2_a_2 = a[2];
assign u_rca5_fa2_b_2 = b[2];
assign u_rca5_fa2_u_rca5_fa1_y4 = u_rca5_fa1_y4[2];
assign u_rca5_fa2_y0 = u_rca5_fa2_a_2 ^ u_rca5_fa2_b_2;
assign u_rca5_fa2_y1 = u_rca5_fa2_a_2 & u_rca5_fa2_b_2;
assign u_rca5_fa2_y2 = u_rca5_fa2_y0 ^ u_rca5_fa2_u_rca5_fa1_y4;
assign u_rca5_fa2_y3 = u_rca5_fa2_y0 & u_rca5_fa2_u_rca5_fa1_y4;
assign u_rca5_fa2_y4 = u_rca5_fa2_y1 | u_rca5_fa2_y3;
assign u_rca5_fa3_a_3 = a[3];
assign u_rca5_fa3_b_3 = b[3];
assign u_rca5_fa3_u_rca5_fa2_y4 = u_rca5_fa2_y4[3];
assign u_rca5_fa3_y0 = u_rca5_fa3_a_3 ^ u_rca5_fa3_b_3;
assign u_rca5_fa3_y1 = u_rca5_fa3_a_3 & u_rca5_fa3_b_3;
assign u_rca5_fa3_y2 = u_rca5_fa3_y0 ^ u_rca5_fa3_u_rca5_fa2_y4;
assign u_rca5_fa3_y3 = u_rca5_fa3_y0 & u_rca5_fa3_u_rca5_fa2_y4;
assign u_rca5_fa3_y4 = u_rca5_fa3_y1 | u_rca5_fa3_y3;
assign u_rca5_fa4_a_4 = a[4];
assign u_rca5_fa4_b_4 = b[4];
assign u_rca5_fa4_u_rca5_fa3_y4 = u_rca5_fa3_y4[4];
assign u_rca5_fa4_y0 = u_rca5_fa4_a_4 ^ u_rca5_fa4_b_4;
assign u_rca5_fa4_y1 = u_rca5_fa4_a_4 & u_rca5_fa4_b_4;
assign u_rca5_fa4_y2 = u_rca5_fa4_y0 ^ u_rca5_fa4_u_rca5_fa3_y4;
assign u_rca5_fa4_y3 = u_rca5_fa4_y0 & u_rca5_fa4_u_rca5_fa3_y4;
assign u_rca5_fa4_y4 = u_rca5_fa4_y1 | u_rca5_fa4_y3;
assign out[0] = u_rca5_ha_y0;
assign out[1] = u_rca5_fa1_y2;
assign out[2] = u_rca5_fa2_y2;
assign out[3] = u_rca5_fa3_y2;
assign out[4] = u_rca5_fa4_y2;
assign out[5] = u_rca5_fa4_y4;
endmodule

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module u_rca8(input [7:0] a, input [7:0] b, output [8:0] out);
wire u_rca8_ha_a_0;
wire u_rca8_ha_b_0;
wire u_rca8_ha_y0;
wire u_rca8_ha_y1;
wire u_rca8_fa1_a_1;
wire u_rca8_fa1_b_1;
wire u_rca8_fa1_y0;
wire u_rca8_fa1_y1;
wire u_rca8_fa1_u_rca8_ha_y1;
wire u_rca8_fa1_y2;
wire u_rca8_fa1_y3;
wire u_rca8_fa1_y4;
wire u_rca8_fa2_a_2;
wire u_rca8_fa2_b_2;
wire u_rca8_fa2_y0;
wire u_rca8_fa2_y1;
wire u_rca8_fa2_u_rca8_fa1_y4;
wire u_rca8_fa2_y2;
wire u_rca8_fa2_y3;
wire u_rca8_fa2_y4;
wire u_rca8_fa3_a_3;
wire u_rca8_fa3_b_3;
wire u_rca8_fa3_y0;
wire u_rca8_fa3_y1;
wire u_rca8_fa3_u_rca8_fa2_y4;
wire u_rca8_fa3_y2;
wire u_rca8_fa3_y3;
wire u_rca8_fa3_y4;
wire u_rca8_fa4_a_4;
wire u_rca8_fa4_b_4;
wire u_rca8_fa4_y0;
wire u_rca8_fa4_y1;
wire u_rca8_fa4_u_rca8_fa3_y4;
wire u_rca8_fa4_y2;
wire u_rca8_fa4_y3;
wire u_rca8_fa4_y4;
wire u_rca8_fa5_a_5;
wire u_rca8_fa5_b_5;
wire u_rca8_fa5_y0;
wire u_rca8_fa5_y1;
wire u_rca8_fa5_u_rca8_fa4_y4;
wire u_rca8_fa5_y2;
wire u_rca8_fa5_y3;
wire u_rca8_fa5_y4;
wire u_rca8_fa6_a_6;
wire u_rca8_fa6_b_6;
wire u_rca8_fa6_y0;
wire u_rca8_fa6_y1;
wire u_rca8_fa6_u_rca8_fa5_y4;
wire u_rca8_fa6_y2;
wire u_rca8_fa6_y3;
wire u_rca8_fa6_y4;
wire u_rca8_fa7_a_7;
wire u_rca8_fa7_b_7;
wire u_rca8_fa7_y0;
wire u_rca8_fa7_y1;
wire u_rca8_fa7_u_rca8_fa6_y4;
wire u_rca8_fa7_y2;
wire u_rca8_fa7_y3;
wire u_rca8_fa7_y4;
assign u_rca8_ha_a_0 = a[0];
assign u_rca8_ha_b_0 = b[0];
assign u_rca8_ha_y0 = u_rca8_ha_a_0 ^ u_rca8_ha_b_0;
assign u_rca8_ha_y1 = u_rca8_ha_a_0 & u_rca8_ha_b_0;
assign u_rca8_fa1_a_1 = a[1];
assign u_rca8_fa1_b_1 = b[1];
assign u_rca8_fa1_u_rca8_ha_y1 = u_rca8_ha_y1[1];
assign u_rca8_fa1_y0 = u_rca8_fa1_a_1 ^ u_rca8_fa1_b_1;
assign u_rca8_fa1_y1 = u_rca8_fa1_a_1 & u_rca8_fa1_b_1;
assign u_rca8_fa1_y2 = u_rca8_fa1_y0 ^ u_rca8_fa1_u_rca8_ha_y1;
assign u_rca8_fa1_y3 = u_rca8_fa1_y0 & u_rca8_fa1_u_rca8_ha_y1;
assign u_rca8_fa1_y4 = u_rca8_fa1_y1 | u_rca8_fa1_y3;
assign u_rca8_fa2_a_2 = a[2];
assign u_rca8_fa2_b_2 = b[2];
assign u_rca8_fa2_u_rca8_fa1_y4 = u_rca8_fa1_y4[2];
assign u_rca8_fa2_y0 = u_rca8_fa2_a_2 ^ u_rca8_fa2_b_2;
assign u_rca8_fa2_y1 = u_rca8_fa2_a_2 & u_rca8_fa2_b_2;
assign u_rca8_fa2_y2 = u_rca8_fa2_y0 ^ u_rca8_fa2_u_rca8_fa1_y4;
assign u_rca8_fa2_y3 = u_rca8_fa2_y0 & u_rca8_fa2_u_rca8_fa1_y4;
assign u_rca8_fa2_y4 = u_rca8_fa2_y1 | u_rca8_fa2_y3;
assign u_rca8_fa3_a_3 = a[3];
assign u_rca8_fa3_b_3 = b[3];
assign u_rca8_fa3_u_rca8_fa2_y4 = u_rca8_fa2_y4[3];
assign u_rca8_fa3_y0 = u_rca8_fa3_a_3 ^ u_rca8_fa3_b_3;
assign u_rca8_fa3_y1 = u_rca8_fa3_a_3 & u_rca8_fa3_b_3;
assign u_rca8_fa3_y2 = u_rca8_fa3_y0 ^ u_rca8_fa3_u_rca8_fa2_y4;
assign u_rca8_fa3_y3 = u_rca8_fa3_y0 & u_rca8_fa3_u_rca8_fa2_y4;
assign u_rca8_fa3_y4 = u_rca8_fa3_y1 | u_rca8_fa3_y3;
assign u_rca8_fa4_a_4 = a[4];
assign u_rca8_fa4_b_4 = b[4];
assign u_rca8_fa4_u_rca8_fa3_y4 = u_rca8_fa3_y4[4];
assign u_rca8_fa4_y0 = u_rca8_fa4_a_4 ^ u_rca8_fa4_b_4;
assign u_rca8_fa4_y1 = u_rca8_fa4_a_4 & u_rca8_fa4_b_4;
assign u_rca8_fa4_y2 = u_rca8_fa4_y0 ^ u_rca8_fa4_u_rca8_fa3_y4;
assign u_rca8_fa4_y3 = u_rca8_fa4_y0 & u_rca8_fa4_u_rca8_fa3_y4;
assign u_rca8_fa4_y4 = u_rca8_fa4_y1 | u_rca8_fa4_y3;
assign u_rca8_fa5_a_5 = a[5];
assign u_rca8_fa5_b_5 = b[5];
assign u_rca8_fa5_u_rca8_fa4_y4 = u_rca8_fa4_y4[5];
assign u_rca8_fa5_y0 = u_rca8_fa5_a_5 ^ u_rca8_fa5_b_5;
assign u_rca8_fa5_y1 = u_rca8_fa5_a_5 & u_rca8_fa5_b_5;
assign u_rca8_fa5_y2 = u_rca8_fa5_y0 ^ u_rca8_fa5_u_rca8_fa4_y4;
assign u_rca8_fa5_y3 = u_rca8_fa5_y0 & u_rca8_fa5_u_rca8_fa4_y4;
assign u_rca8_fa5_y4 = u_rca8_fa5_y1 | u_rca8_fa5_y3;
assign u_rca8_fa6_a_6 = a[6];
assign u_rca8_fa6_b_6 = b[6];
assign u_rca8_fa6_u_rca8_fa5_y4 = u_rca8_fa5_y4[6];
assign u_rca8_fa6_y0 = u_rca8_fa6_a_6 ^ u_rca8_fa6_b_6;
assign u_rca8_fa6_y1 = u_rca8_fa6_a_6 & u_rca8_fa6_b_6;
assign u_rca8_fa6_y2 = u_rca8_fa6_y0 ^ u_rca8_fa6_u_rca8_fa5_y4;
assign u_rca8_fa6_y3 = u_rca8_fa6_y0 & u_rca8_fa6_u_rca8_fa5_y4;
assign u_rca8_fa6_y4 = u_rca8_fa6_y1 | u_rca8_fa6_y3;
assign u_rca8_fa7_a_7 = a[7];
assign u_rca8_fa7_b_7 = b[7];
assign u_rca8_fa7_u_rca8_fa6_y4 = u_rca8_fa6_y4[7];
assign u_rca8_fa7_y0 = u_rca8_fa7_a_7 ^ u_rca8_fa7_b_7;
assign u_rca8_fa7_y1 = u_rca8_fa7_a_7 & u_rca8_fa7_b_7;
assign u_rca8_fa7_y2 = u_rca8_fa7_y0 ^ u_rca8_fa7_u_rca8_fa6_y4;
assign u_rca8_fa7_y3 = u_rca8_fa7_y0 & u_rca8_fa7_u_rca8_fa6_y4;
assign u_rca8_fa7_y4 = u_rca8_fa7_y1 | u_rca8_fa7_y3;
assign out[0] = u_rca8_ha_y0;
assign out[1] = u_rca8_fa1_y2;
assign out[2] = u_rca8_fa2_y2;
assign out[3] = u_rca8_fa3_y2;
assign out[4] = u_rca8_fa4_y2;
assign out[5] = u_rca8_fa5_y2;
assign out[6] = u_rca8_fa6_y2;
assign out[7] = u_rca8_fa7_y2;
assign out[8] = u_rca8_fa7_y4;
endmodule

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Tests/Verilog_circuits/Logic_gates/and_gate.v Normal file
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module _and_gate(input _a, input _b, output _y0);
assign _y0 = _a & _b;
endmodule

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Tests/Verilog_circuits/Logic_gates/nand_gate.v Normal file
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module _nand_gate(input _a, input _b, output _y0);
assign _y0 = ~(_a & _b);
endmodule

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Tests/Verilog_circuits/Logic_gates/nor_gate.v Normal file
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module _nor_gate(input _a, input _b, output _y0);
assign _y0 = ~(_a | _b);
endmodule

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Tests/Verilog_circuits/Logic_gates/not_gate.v Normal file
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module _not_gate(input _a, output _y0);
assign _y0 = ~_a;
endmodule

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Tests/Verilog_circuits/Logic_gates/or_gate.v Normal file
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module _or_gate(input _a, input _b, output _y0);
assign _y0 = _a | _b;
endmodule

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Tests/Verilog_circuits/Logic_gates/xnor_gate.v Normal file
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module _xnor_gate(input _a, input _b, output _y0);
assign _y0 = ~(_a ^ _b);
endmodule

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Tests/Verilog_circuits/Logic_gates/xor_gate.v Normal file
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module _xor_gate(input _a, input _b, output _y0);
assign _y0 = _a ^ _b;
endmodule