Test commit

2021-03-22 00:31:59 +01:00 · 2021-03-22 00:31:59 +01:00 · 8df8e72810
commit 8df8e72810
parent 792d0c5db1
1 changed files with 0 additions and 1 deletions
--- a/arithmetic_circuits_generator.py
+++ b/arithmetic_circuits_generator.py
@ -29,7 +29,6 @@ if __name__ == "__main__":
    #arrmul.get_v_code_flat(open("arrmul_test.v", "w"))
    #arrmul.get_blif_code_flat(open("arrmul_test.blif", "w"))
    
-    
    w1 = wire(name="a")
    w2 = wire(name="b")
    w3 = wire(name="cin")