Added signed rca circuit.
This commit is contained in:
honzastor
parent
ee73047199
commit
de127e8c46
@ -3,13 +3,16 @@ from logic_gates_generator import and_gate, xor_gate, or_gate
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import sys
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# ARITMETICKE OBVODY
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""" ARITHMETIC CIRCUITS """
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class arithmetic_circuit():
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def __init__(self):
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self.components = []
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self.circuit_wires = []
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self.c_data_type = "uint64_t"
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# TODO delete?
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self.input_N = 0
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self.carry_out_gate = None
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self.sum_out_gates = []
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@ -26,12 +29,13 @@ class arithmetic_circuit():
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def get_carry_wire(self):
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return self.out.get_wire(1)
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# FLAT C GENERATION #
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@staticmethod
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def get_includes_c():
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return f"#include <stdio.h>\n#include <stdint.h>\n\n"
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def get_prototype_c(self):
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return f"{self.c_data_type} {self.prefix}({self.c_data_type} {self.a.prefix}, {self.c_data_type} {self.b.prefix})" + "{" + '\n'
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return f"uint64_t {self.prefix}({self.c_data_type} {self.a.prefix}, {self.c_data_type} {self.b.prefix})" + "{" + '\n'
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def get_declaration_c(self):
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return f"".join([c.get_declaration_c() for c in self.components])
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@ -45,18 +49,21 @@ class arithmetic_circuit():
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def get_function_carry_c(self):
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return f"{self.get_previous_component().get_function_carry_c(offset=self.out.N-1)}"
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# Generovani aritmetickeho obvodu do jazyka C
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# Generating flat C code representation of circuit
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def get_c_code(self, file_object):
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file_object.write(self.get_includes_c())
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file_object.write(self.get_prototype_c())
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file_object.write(self.out.get_declaration_c())
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file_object.write(self.get_declaration_c())
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file_object.write(self.get_initialization_c())
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file_object.write(self.get_declaration_c()+"\n")
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file_object.write(self.get_initialization_c()+"\n")
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file_object.write(self.get_function_sum_c())
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file_object.write(self.get_function_carry_c())
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file_object.write(f" return {self.out.prefix}"+";\n}")
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file_object.close()
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# HIERARCHICAL C GENERATION #
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# TODO
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class half_adder(arithmetic_circuit):
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def __init__(self, a: wire, b: wire, prefix: str = "ha"):
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@ -65,25 +72,28 @@ class half_adder(arithmetic_circuit):
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self.prefix = prefix
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self.a = a
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self.b = b
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# 2 draty pro vystupy komponenty (sum, cout)
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# 2 wires for component's bus output (sum, cout)
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self.out = bus("out", 2)
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# Sum
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# XOR hradlo pro vypocet jednobitového souctu (sum)
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# XOR gate for calculation of 1-bit sum
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obj_xor_gate = xor_gate(a, b, prefix, outid=0)
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self.add_component(obj_xor_gate)
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self.out.connect(0, obj_xor_gate.output)
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# Cout
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# AND hradlo pro vypocet jednobitoveho priznaku prenosu do vyssiho radu (cout)jednobitového souctu (sum)
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# AND gate for calculation of 1-bit cout
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obj_and_gate = and_gate(a, b, prefix, outid=1)
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self.add_component(obj_and_gate)
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self.out.connect(1, obj_and_gate.output)
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# FLAT C GENERATION #
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# Half adder function prototype with two inputs
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def get_prototype_c(self):
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return f"{self.c_data_type} {self.prefix}({self.c_data_type} {self.a.name}, {self.c_data_type} {self.b.name})" + "{" + '\n'
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# Ziskani vsech unikatnich vodicu obvodu ze vsech hradel k zajisteni neopakujicich se deklaraci stejnych vodicu
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# Obtaining list of all the unique circuit wires from all contained logic gates
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# to ensure non-recurring declaration of same wires
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def get_declaration_c(self):
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for component in self.components:
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if not [item for item in self.circuit_wires if item[1] == component.a.name]:
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@ -95,10 +105,10 @@ class half_adder(arithmetic_circuit):
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if not [item for item in self.circuit_wires if item[1] == component.output.name]:
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self.circuit_wires.append((component.output, component.output.name))
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# Unikatni deklarace vsech propoju obvodu
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# Unique declaration of all circuit's interconnections
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return "".join([c[0].get_declaration_c() for c in self.circuit_wires])
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# Inicializace hodnot vodicu polovicni scitacky
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# Half adder wires values initialization
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def get_initialization_c(self):
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return f" {self.components[0].a.name} = {self.a.get_wire_value_c(offset=self.a.index)};\n" + \
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f" {self.components[0].b.name} = {self.b.get_wire_value_c(offset=self.b.index)};\n" + \
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@ -120,23 +130,23 @@ class full_adder(arithmetic_circuit):
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self.a = a
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self.b = b
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self.c = c
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# 2 draty pro vystupy komponenty (sum, cout)
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# 2 wires for component's bus output (sum, cout)
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self.out = bus("out", 2)
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# PG logika
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# PG logic
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propagate_xor_gate1 = xor_gate(a, b, prefix, outid=0)
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self.add_component(propagate_xor_gate1)
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generate_and_gate1 = and_gate(a, b, prefix, outid=1)
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self.add_component(generate_and_gate1)
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# Sum
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# XOR hradlo pro vypocet jednobitového souctu (sum)
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# XOR gate for calculation of 1-bit sum
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obj_xor_gate2 = xor_gate(propagate_xor_gate1.output, c, prefix, outid=2)
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self.add_component(obj_xor_gate2)
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self.out.connect(0, obj_xor_gate2.output)
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# Cout
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# AND hradlo pro vypocet jednobitoveho priznaku prenosu do vyssiho radu (cout)jednobitového souctu (sum)
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# AND gate for calculation of 1-bit cout
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obj_and_gate2 = and_gate(propagate_xor_gate1.output, c, prefix, outid=3)
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self.add_component(obj_and_gate2)
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@ -145,14 +155,17 @@ class full_adder(arithmetic_circuit):
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self.out.connect(1, obj_or_gate.output)
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# TODO nechat do budoucna?
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# TODO delete or leave?
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self.propagate = propagate_xor_gate1.output
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self.generate = generate_and_gate1.output
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# 3 vstupy spolu s carry in
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# FLAT C GENERATION #
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# Full adder function prototype with three inputs
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def get_prototype_c(self):
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return f"{self.c_data_type} {self.prefix}({self.c_data_type} {self.a.name}, {self.c_data_type} {self.b.name}, {self.c_data_type} {self.c.name})" + "{" + '\n'
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# Obtaining list of all the unique circuit wires from all contained logic gates
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# to ensure non-recurring declaration of same wires
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def get_declaration_c(self):
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for component in self.components:
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if not [item for item in self.circuit_wires if item[1] == component.a.name]:
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@ -164,10 +177,10 @@ class full_adder(arithmetic_circuit):
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if not [item for item in self.circuit_wires if item[1] == component.output.name]:
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self.circuit_wires.append((component.output, component.output.name))
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# Unikatni deklarace vsech propoju obvodu
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# Unique declaration of all circuit's interconnections
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return "".join([c[0].get_declaration_c() for c in self.circuit_wires])
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# Inicializace hodnot vodicu uplne scitacky
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# Full adder wires values initialization
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def get_initialization_c(self):
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return f" {self.components[0].a.name} = {self.a.get_wire_value_c(offset=self.a.index)};\n" + \
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f" {self.components[0].b.name} = {self.b.get_wire_value_c(offset=self.b.index)};\n" + \
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@ -185,44 +198,123 @@ class full_adder(arithmetic_circuit):
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return f" {self.out.prefix} |= {self.components[4].output.return_wire_value_c(offset = offset)};\n"
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class ripple_carry_adder(arithmetic_circuit):
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def __init__(self, a: bus, b: bus, prefix: str = "rca"):
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class signed_ripple_carry_adder(arithmetic_circuit):
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def __init__(self, a: bus, b: bus, prefix: str = "s_rca"):
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super().__init__()
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N = max(a.N, b.N)
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self.prefix = prefix+str(N)
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self.N = max(a.N, b.N)
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self.c_data_type = "int64_t"
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# Bus sign extension in case buses have different lengths
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a.sign_extend(self.N)
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b.sign_extend(self.N)
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self.a = a
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self.b = b
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if prefix == "s_rca":
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self.prefix = prefix+str(self.N)
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else:
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self.prefix = prefix
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# Vystupni draty pro N souctu a vystupni priznak prenosu do vyssiho radu (cout)
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self.out = bus("out", N+1)
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# Output wires for N sum bits and additional cout bit
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self.out = bus("out", self.N+1)
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# Postupne pridani jednobitovych scitacek
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for input_index in range(N):
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# Prvni je polovicni scitacka
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# Gradual addition of 1-bit adder components
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for input_index in range(self.N):
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# First one is a half adder
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if input_index == 0:
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obj_ha = half_adder(a.get_wire(input_index), b.get_wire(input_index), prefix=self.prefix+"_ha")
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self.add_component(obj_ha)
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self.out.connect(input_index, obj_ha)
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# Rest are full adders
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else:
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obj_fa = full_adder(a.get_wire(input_index), b.get_wire(input_index), self.get_previous_component().get_carry_wire(), prefix=self.prefix+"_fa"+str(input_index))
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self.add_component(obj_fa)
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self.out.connect(input_index, obj_fa.get_sum_wire())
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if input_index == (N-1):
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self.out.connect(N, obj_fa.get_carry_wire())
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if input_index == (self.N-1):
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self.out.connect(self.N, obj_fa.get_carry_wire())
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# Additional XOR gates to ensure correct sign extension in case of sign addition
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sign_xor_1 = xor_gate(self.get_previous_component().a, self.get_previous_component().b, prefix=self.prefix+"_xor_1")
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sign_xor_2 = xor_gate(sign_xor_1.output, self.get_previous_component().get_carry_wire(), prefix=self.prefix+"_xor_2")
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self.add_component(sign_xor_1)
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self.add_component(sign_xor_2)
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# FLAT C GENERATION #
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# Initialization of 1-bit adders and sign extension XOR gates
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def get_initialization_c(self):
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return f"".join([c.get_initialization_c() for c in self.components[:-2]]) + \
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f" {self.components[-2].a.name} = {self.a.get_wire_value_c(offset=self.N-1)};\n" + \
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f" {self.components[-2].b.name} = {self.b.get_wire_value_c(offset=self.N-1)};\n" + \
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f" {self.components[-2].output.name} = {self.components[-2].get_initialization_c()};\n" + \
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f" {self.components[-1].a.name} = {self.components[-2].output.get_wire_value_c()};\n" + \
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f" {self.components[-1].b.name} = {self.components[-3].get_carry_wire().get_wire_value_c()};\n" + \
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f" {self.components[-1].output.name} = {self.components[-1].get_initialization_c()};\n"
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def get_function_sum_c(self):
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return "".join([c.get_function_sum_c(self.components.index(c)) for c in self.components[:-2]])
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def get_function_carry_c(self):
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return f" {self.out.prefix} |= {self.get_previous_component().output.return_wire_value_c(offset = self.N)};\n"
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class unsigned_ripple_carry_adder(arithmetic_circuit):
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def __init__(self, a: bus, b: bus, prefix: str = "u_rca"):
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super().__init__()
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self.N = max(a.N, b.N)
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# Bus sign extension in case buses have different lengths
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a.sign_extend(self.N)
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b.sign_extend(self.N)
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self.a = a
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self.b = b
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if prefix == "u_rca":
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self.prefix = prefix+str(self.N)
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else:
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self.prefix = prefix
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# Output wires for N sum bits and additional cout bit
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self.out = bus("out", self.N+1)
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# Gradual addition of 1-bit adder components
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for input_index in range(self.N):
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# First one is a half adder
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if input_index == 0:
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obj_ha = half_adder(a.get_wire(input_index), b.get_wire(input_index), prefix=self.prefix+"_ha")
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self.add_component(obj_ha)
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self.out.connect(input_index, obj_ha)
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# Rest are full adders
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else:
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obj_fa = full_adder(a.get_wire(input_index), b.get_wire(input_index), self.get_previous_component().get_carry_wire(), prefix=self.prefix+"_fa"+str(input_index))
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self.add_component(obj_fa)
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self.out.connect(input_index, obj_fa.get_sum_wire())
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if input_index == (self.N-1):
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self.out.connect(self.N, obj_fa.get_carry_wire())
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if __name__ == "__main__":
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# Vytvoreni obvodu 8 bitove postupne scitacky
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a = bus(N=8, prefix="a")
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b = bus(N=8, prefix="b")
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rca = signed_ripple_carry_adder(a, b)
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rca.get_c_code(open("s_rca8.c", "w"))
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w1 = wire(name="a")
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w2 = wire(name="b")
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w3 = wire(name="cin")
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fa = full_adder(w1, w2, w3)
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fa.get_c_code(open("fa.c", "w"))
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"""
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# Generation of 8-bit rca
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a = bus(N=8, prefix="a")
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b = bus(N=8, prefix="b")
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rca = ripple_carry_adder(a, b)
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# Export do jazyka C (flat)
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# Export to C code (flat) and save to file
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rca.get_c_code(open("rca_8.c", "w"))
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# Vytvoreni logickeho hradla OR
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# Hodnoty pouze pro otestovani funcnosti v Pythonu
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# Generation of OR logic gate
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# Values just for testing functionality within Python
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a1 = wire(name="a", value=1)
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b1 = wire(name="b", value=0)
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xor = xor_gate(a1, b1)
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# Vypis v jazyke C (flat) na standardni vystup
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# Export to C code (flat) and display to stdout
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xor.get_c_code(sys.stdout)
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"""
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@ -1,13 +1,16 @@
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from wire_components import wire
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# KOMPONENTY HRADEL
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""" LOGIC GATE COMPONENTS """
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class logic_gate():
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def __init__(self, a: wire, b: wire, prefix: str = "w"):
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self.a = wire(prefix+"_"+a.name.replace(prefix+"_", ''), a.value)
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self.b = wire(prefix+"_"+b.name.replace(prefix+"_", ''), b.value)
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self.prefix = prefix
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# FLAT C GENERATION #
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@staticmethod
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def get_includes_c():
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return f"#include <stdio.h>\n#include <stdint.h>\n\n"
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@ -26,15 +29,19 @@ class logic_gate():
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self.b.name = self.b.name.replace(self.prefix+"_", '')
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return f"{self.a.get_wire_value_c()} {self.operator} {self.b.get_wire_value_c(0)}"
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# Generovani samostatneho obvodu logickeho hradla do jazyka C
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# Generating flat C code representation of separate logic gate
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# (i.e. not as a component of bigger circuit)
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def get_c_code(self, file_object):
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file_object.write(self.get_includes_c())
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file_object.write(self.get_prototype_c())
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file_object.write(" return "+(self.get_function_c())+";\n}")
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file_object.close()
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# HIERARCHICAL C GENERATION #
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# TODO
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# Jednovstupa
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# Single-input
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class not_gate(logic_gate):
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def __init__(self, a: wire, prefix: str = "w", outid: int = 0):
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self.gate_type = 'not_gate'
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@ -61,7 +68,7 @@ class not_gate(logic_gate):
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return f"{self.operator}{self.a.get_wire_value_c()} & 0x01 << 0"
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# Dvouvstupa
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# Two-input
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class and_gate(logic_gate):
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def __init__(self, a: wire, b: wire, prefix: str = "w", outid: int = 0):
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super().__init__(a, b, prefix)
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@ -1,4 +1,4 @@
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# KOMPONENTY PROPOJU
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""" WIRE COMPONENTS """
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class wire():
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@ -18,7 +18,6 @@ class wire():
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class bus():
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# Inicializace sbernice
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def __init__(self, prefix: str = "bus", N: int = 1):
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self.bus = [wire(name=prefix, index=i) for i in range(N)]
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self.prefix = prefix
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@ -27,13 +26,13 @@ class bus():
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def __index__(self, wire):
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return self.bus.index(wire)
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# Pripojeni vystupniho vodice vnitrni komponenty na vstup jine komponenty
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# (nebo drat vystupni sbernice obvodu)
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# Connecting output wire of the inner circuit component to the input of another component
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# (or to the wire of the circuit's output bus)
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def connect(self, out_wire_index: int, inner_component_out_wire: wire):
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self.bus[out_wire_index] = inner_component_out_wire
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def get_wire_value_c(self, offset: int = 0):
|
||||
self.bus[offset].get_wire_value_c(offset)
|
||||
return self.bus[offset].get_wire_value_c(offset=offset)
|
||||
|
||||
def return_wire_value_c(self, offset: int = 0):
|
||||
self.bus[offset].return_wire_value_c(offset)
|
||||
@ -46,3 +45,7 @@ class bus():
|
||||
|
||||
def get_wire(self, wire_index: int):
|
||||
return self.bus[wire_index]
|
||||
|
||||
def sign_extend(self, N: int):
|
||||
self.bus = [wire(name=self.prefix, index=i) for i in range(N)]
|
||||
self.N = N
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user