Added truncated multiplier circuit implementation. Needs testing.
This commit is contained in:
Honza
parent
c8ed08691f
commit
f830029c54
@ -11,5 +11,6 @@ from .one_bit_circuits import (
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from .multi_bit_circuits import (
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adders,
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multipliers,
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approximate_multipliers,
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dividers
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)
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@ -33,18 +33,20 @@ class MultiplierCircuit(ArithmeticCircuit):
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super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=out_N, **kwargs)
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# Array multipliers
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def get_previous_partial_product(self, a_index: int, b_index: int):
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def get_previous_partial_product(self, a_index: int, b_index: int, horizontal_break: int = 0, vertical_break: int=0):
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"""Used in array multipliers to get previous row's component output wires for further connection to another component's input.
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Args:
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a_index (int): First input wire index.
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b_index (int): Second input wire index.
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horizontal_break (int, optional): Specifies horizontal break used in truncated multiplier circuit creation. Defaults to 0.
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vertical_break (int, optional): Specifies vertical break used in truncated multiplier circuit creation. Defaults to 0.
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Returns:
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Wire: Previous row's component wire of corresponding pp.
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"""
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# To get the index of previous row's connecting adder and its generated pp
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index = ((b_index-2) * (self.N*2)) + ((self.N-1)+2*(a_index+2))
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index = ((b_index-horizontal_break-2) * ((self.N-vertical_break)*2)) + ((self.N-vertical_break-1)+2*(a_index-vertical_break+2))
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# Get carry wire as input for the last adder in current row
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if a_index == self.N-1:
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@ -0,0 +1,4 @@
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from ariths_gen.multi_bit_circuits.approximate_multipliers.truncated_multiplier import (
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UnsignedTruncatedMultiplier,
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SignedTruncatedMultiplier
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)
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@ -0,0 +1,288 @@
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from ariths_gen.wire_components import (
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Wire,
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ConstantWireValue0,
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ConstantWireValue1,
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Bus
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)
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from ariths_gen.core.arithmetic_circuits import (
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ArithmeticCircuit,
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MultiplierCircuit
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)
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from ariths_gen.one_bit_circuits.one_bit_components import (
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HalfAdder,
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FullAdder,
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FullAdderPG
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)
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from ariths_gen.one_bit_circuits.logic_gates import (
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AndGate,
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NandGate,
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OrGate,
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NorGate,
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XorGate,
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XnorGate,
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NotGate
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)
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from ariths_gen.multi_bit_circuits.multipliers import(
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UnsignedArrayMultiplier,
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SignedArrayMultiplier
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)
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class UnsignedTruncatedMultiplier(MultiplierCircuit):
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"""Class representing unsigned truncated multiplier.
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TODO
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Unsigned truncated multiplier represents N-bit multiplier composed of
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many AND gates and half/full adders to calculate partial products and
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gradually sum them.
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Downside is its rather big area because it is composed of many logic gates.
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TODO
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```
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A3B0 A2B0 A1B0 A0B0
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│ │ │ │ │ │ │ │
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┌▼─▼┐ ┌▼─▼┐ ┌▼─▼┐ ┌▼─▼┐
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│AND│ │AND│ │AND│ │AND│
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└┬──┘ └┬──┘ └┬──┘ └─┬─┘
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A3B1 │ A2B1 │ A1B1 │ A0B1 │
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┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │
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│AND│ │ │AND│ │ │AND│ │ │AND│ │
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└┬──┘ │ └┬──┘ │ └┬──┘ │ └┬──┘ │
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│ │ │ │ │ │ │ │
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┌───▼┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ │
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│ │ │ │ │ │ │ │ │
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┌───────┤ HA │◄──┤ FA │◄──┤ FA │◄──┤ HA │ │
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│ │ │ │ │ │ │ │ │ │
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│ └┬───┘ └┬───┘ └┬───┘ └─┬──┘ │
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│ A3B2 │ A2B2 │ A1B2 │ A0B2 │ │
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│ ┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ │
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│ │AND│ │ │AND│ │ │AND│ │ │AND│ │ │
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│ └┬──┘ │ └┬──┘ │ └┬──┘ │ └┬──┘ │ │
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│ │ │ │ │ │ │ │ │ │
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┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ │ │
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│ │ │ │ │ │ │ │ │ │
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┌───────┤ FA │◄──┤ FA │◄──┤ FA │◄──┤ HA │ │ │
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│ │ │ │ │ │ │ │ │ │ │
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│ └┬───┘ └┬───┘ └┬───┘ └─┬──┘ │ │
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│ A3B3 │ A2B3 │ A1B3 │ A0B3 │ │ │
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│ ┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ │ │
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│ │AND│ │ │AND│ │ │AND│ │ │AND│ │ │ │
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│ └┬──┘ │ └┬──┘ │ └┬──┘ │ └┬──┘ │ │ │
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│ │ │ │ │ │ │ │ │ │ │
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┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ │ │ │
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│ │ │ │ │ │ │ │ │ │ │
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┌──────┤ FA │◄──┤ FA │◄──┤ FA │◄──┤ HA │ │ │ │
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│ │ │ │ │ │ │ │ │ │ │ │
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│ └─┬──┘ └─┬──┘ └─┬──┘ └─┬──┘ │ │ │
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│ │ │ │ │ │ │ │
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▼ ▼ ▼ ▼ ▼ ▼ ▼ ▼
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P7 P6 P5 P4 P3 P2 P1 P0
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```
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Description of the __init__ method.
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Args:
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a (Bus): First input bus.
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b (Bus): Second input bus.
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horizontal_break (int, optional): Specifies horizontal break used in truncated multiplier circuit creation. Defaults to 0.
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vertical_break (int, optional): Specifies vertical break used in truncated multiplier circuit creation. Defaults to 0.
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prefix (str, optional): Prefix name of unsigned truncated multiplier. Defaults to "".
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name (str, optional): Name of unsigned truncated multiplier. Defaults to "u_tm".
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"""
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def __init__(self, a: Bus, b: Bus, horizontal_break: int = 0, vertical_break: int = 0, prefix: str = "", name: str = "u_tm", **kwargs):
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# NOTE: If horizontal/vertical break is specified as 0 the final circuit is a simple array multiplier
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self.horizontal_break = horizontal_break
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self.vertical_break = vertical_break
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self.N = max(a.N, b.N)
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super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, **kwargs)
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# Bus sign extension in case buses have different lengths
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self.a.bus_extend(N=self.N, prefix=a.prefix)
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self.b.bus_extend(N=self.N, prefix=b.prefix)
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break_offsets = horizontal_break + vertical_break
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# Gradual generation of partial products
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for b_multiplier_index in range(self.horizontal_break, self.N):
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for a_multiplicand_index in range(self.vertical_break, self.N):
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# AND gates generation for calculation of partial products
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obj_and = AndGate(self.a.get_wire(a_multiplicand_index), self.b.get_wire(b_multiplier_index), prefix=self.prefix+"_and"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
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self.add_component(obj_and)
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if b_multiplier_index != self.horizontal_break and self.vertical_break != self.N-1:
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if b_multiplier_index == self.horizontal_break + 1:
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previous_product = self.components[a_multiplicand_index + b_multiplier_index - break_offsets].out
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else:
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previous_product = self.get_previous_partial_product(a_index=a_multiplicand_index, b_index=b_multiplier_index, horizontal_break=horizontal_break, vertical_break=vertical_break)
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# HA generation for first 1-bit adder in each row starting from the second one
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if a_multiplicand_index == self.vertical_break:
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obj_adder = HalfAdder(self.get_previous_component().out, previous_product, prefix=self.prefix+"_ha"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
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self.add_component(obj_adder)
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# Product generation
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self.out.connect(b_multiplier_index + self.vertical_break, obj_adder.get_sum_wire())
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# HA generation, last 1-bit adder in second row
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elif a_multiplicand_index == self.N-1 and b_multiplier_index == self.horizontal_break+1:
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obj_adder = HalfAdder(self.get_previous_component().out, self.get_previous_component(number=2).get_carry_wire(), prefix=self.prefix+"_ha"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
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self.add_component(obj_adder)
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# FA generation
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else:
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obj_adder = FullAdder(self.get_previous_component().out, previous_product, self.get_previous_component(number=2).get_carry_wire(), prefix=self.prefix+"_fa"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
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self.add_component(obj_adder)
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# PRODUCT GENERATION
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if (a_multiplicand_index == self.vertical_break and b_multiplier_index == self.horizontal_break) or (self.horizontal_break == self.N-1 or self.vertical_break == self.N-1):
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self.out.connect(a_multiplicand_index + b_multiplier_index, obj_and.out)
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if a_multiplicand_index == self.N-1 and b_multiplier_index == self.N-1:
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self.out.connect(a_multiplicand_index+b_multiplier_index+1, ConstantWireValue0())
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elif b_multiplier_index == self.N-1 and self.horizontal_break != self.N-1 and self.vertical_break != self.N-1:
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self.out.connect(b_multiplier_index + a_multiplicand_index, obj_adder.get_sum_wire())
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if a_multiplicand_index == self.N-1:
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self.out.connect(self.out.N-1, obj_adder.get_carry_wire())
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# Connecting the output bits generated from ommited cells to ground
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if self.horizontal_break >= self.N or self.vertical_break >= self.N:
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[self.out.connect(out_id, ConstantWireValue0()) for out_id in range(self.out.N)]
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else:
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for grounded_out_index in range(0, break_offsets):
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self.out.connect(grounded_out_index, ConstantWireValue0())
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class SignedTruncatedMultiplier(MultiplierCircuit):
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"""Class representing signed truncated multiplier.
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TODO
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Signed array multiplier represents N-bit multiplier composed of
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many AND/NAND gates and half/full adders to calculate partial products and
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gradually sum them.
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Downside is its rather big area because it is composed of many logic gates.
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TODO
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```
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A3B0 A2B0 A1B0 A0B0
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│ │ │ │ │ │ │ │
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┌▼─▼─┐ ┌▼─▼┐ ┌▼─▼┐ ┌▼─▼┐
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│NAND│ │AND│ │AND│ │AND│
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└┬───┘ └┬──┘ └┬──┘ └─┬─┘
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A3B1 │ A2B1 │ A1B1 │ A0B1 │
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┌▼─▼─┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │
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│NAND│ │ │AND│ │ │AND│ │ │AND│ │
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1 └┬───┘ │ └┬──┘ │ └┬──┘ │ └┬──┘ │
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│ │ │ │ │ │ │ │ │
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┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ │
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│ │ │ │ │ │ │ │ │
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┌───────┤ FA │◄──┤ FA │◄──┤ FA │◄──┤ HA │ │
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│ │ │ │ │ │ │ │ │ │
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│ └┬───┘ └┬───┘ └┬───┘ └─┬──┘ │
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│ A3B2 │ A2B2 │ A1B2 │ A0B2 │ │
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│ ┌▼─▼─┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ │
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│ │NAND│ │ │AND│ │ │AND│ │ │AND│ │ │
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│ └┬───┘ │ └┬──┘ │ └┬──┘ │ └┬──┘ │ │
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│ │ │ │ │ │ │ │ │ │
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┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ │ │
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│ │ │ │ │ │ │ │ │ │
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┌───────┤ FA │◄──┤ FA │◄──┤ FA │◄──┤ HA │ │ │
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│ │ │ │ │ │ │ │ │ │ │
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│ └┬───┘ └┬───┘ └┬───┘ └─┬──┘ │ │
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│ A3B3 │ A2B3 │ A1B3 │ A0B3 │ │ │
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│ ┌▼─▼┐ │ ┌▼─▼─┐ │ ┌▼─▼─┐ │ ┌▼─▼─┐ │ │ │
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│ │AND│ │ │NAND│ │ │NAND│ │ │NAND│ │ │ │
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1 │ └┬──┘ │ └┬───┘ │ └┬───┘ │ └┬───┘ │ │ │
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│ │ │ │ │ │ │ │ │ │ │ │
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┌─▼──┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ │ │ │
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│ │ │ │ │ │ │ │ │ │ │ │ │
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│XOR │◄──┤ FA │◄──┤ FA │◄──┤ FA │◄──┤ HA │ │ │ │
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│ │ │ │ │ │ │ │ │ │ │ │ │
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└─┬──┘ └─┬──┘ └─┬──┘ └─┬──┘ └─┬──┘ │ │ │
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│ │ │ │ │ │ │ │
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▼ ▼ ▼ ▼ ▼ ▼ ▼ ▼
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P7 P6 P5 P4 P3 P2 P1 P0
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```
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Description of the __init__ method.
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Args:
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a (Bus): First input bus.
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b (Bus): Second input bus.
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horizontal_break (int, optional): Specifies horizontal break used in signed truncated multiplier circuit creation. Defaults to 0.
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vertical_break (int, optional): Specifies vertical break used in signed truncated multiplier circuit creation. Defaults to 0.
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prefix (str, optional): Prefix name of signed truncated multiplier. Defaults to "".
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name (str, optional): Name of signed truncated multiplier. Defaults to "s_tm".
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"""
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def __init__(self, a: Bus, b: Bus, horizontal_break: int = 0, vertical_break: int = 0, prefix: str = "", name: str = "s_tm", **kwargs):
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# NOTE: If horizontal/vertical break is specified as 0 the final circuit is a simple array multiplier
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self.horizontal_break = horizontal_break
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self.vertical_break = vertical_break
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self.N = max(a.N, b.N)
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super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, signed=True, **kwargs)
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self.c_data_type = "int64_t"
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# Bus sign extension in case buses have different lengths
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self.a.bus_extend(N=self.N, prefix=a.prefix)
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self.b.bus_extend(N=self.N, prefix=b.prefix)
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break_offsets = horizontal_break + vertical_break
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# Gradual generation of partial products
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for b_multiplier_index in range(self.horizontal_break, self.N):
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for a_multiplicand_index in range(self.vertical_break, self.N):
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# AND and NAND gates generation for calculation of partial products and sign extension
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if (b_multiplier_index == self.N-1 and a_multiplicand_index != self.N-1) or (b_multiplier_index != self.N-1 and a_multiplicand_index == self.N-1):
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obj_nand = NandGate(self.a.get_wire(a_multiplicand_index), self.b.get_wire(b_multiplier_index), prefix=self.prefix+"_nand"+str(a_multiplicand_index)+"_"+str(b_multiplier_index), parent_component=self)
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self.add_component(obj_nand)
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else:
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obj_and = AndGate(self.a.get_wire(a_multiplicand_index), self.b.get_wire(b_multiplier_index), prefix=self.prefix+"_and"+str(a_multiplicand_index)+"_"+str(b_multiplier_index), parent_component=self)
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self.add_component(obj_and)
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if b_multiplier_index != self.horizontal_break and self.vertical_break != self.N-1:
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if b_multiplier_index == self.horizontal_break + 1:
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previous_product = self.components[a_multiplicand_index + b_multiplier_index - break_offsets].out
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else:
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previous_product = self.get_previous_partial_product(a_index=a_multiplicand_index, b_index=b_multiplier_index, horizontal_break=horizontal_break, vertical_break=vertical_break)
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# HA generation for first 1-bit adder in each row starting from the second one
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if a_multiplicand_index == self.vertical_break:
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obj_adder = HalfAdder(self.get_previous_component().out, previous_product, prefix=self.prefix+"_ha"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
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self.add_component(obj_adder)
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# Product generation
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self.out.connect(b_multiplier_index, obj_adder.get_sum_wire())
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# FA generation
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else:
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# Constant wire with value 1 used at the last FA in second row (as one of its inputs) for signed multiplication (based on Baugh Wooley algorithm)
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if a_multiplicand_index == self.N-1 and b_multiplier_index == self.horizontal_break+1:
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previous_product = ConstantWireValue1()
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obj_adder = FullAdder(self.get_previous_component().out, previous_product, self.get_previous_component(number=2).get_carry_wire(), prefix=self.prefix+"_fa"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
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self.add_component(obj_adder)
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# PRODUCT GENERATION
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if (a_multiplicand_index == self.vertical_break and b_multiplier_index == self.horizontal_break) or (self.horizontal_break == self.N-1 or self.vertical_break == self.N-1):
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self.out.connect(a_multiplicand_index + b_multiplier_index, obj_and.out)
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# 1 bit multiplier case
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if a_multiplicand_index == self.N-1 and b_multiplier_index == self.N-1:
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obj_nor = NorGate(ConstantWireValue1(), self.get_previous_component().out, prefix=self.prefix+"_nor_zero_extend", parent_component=self)
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self.add_component(obj_nor)
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self.out.connect(a_multiplicand_index+1, obj_nor.out)
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elif b_multiplier_index == self.N-1 and self.horizontal_break != self.N-1 and self.vertical_break != self.N-1:
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self.out.connect(b_multiplier_index + a_multiplicand_index, obj_adder.get_sum_wire())
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if a_multiplicand_index == self.N-1:
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obj_xor = XorGate(self.get_previous_component().get_carry_wire(), ConstantWireValue1(), prefix=self.prefix+"_xor"+str(a_multiplicand_index+1)+"_"+str(b_multiplier_index), parent_component=self)
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self.add_component(obj_xor)
|
||||
|
||||
self.out.connect(self.out.N-1, obj_xor.out)
|
||||
|
||||
# Connecting the output bits generated from ommited cells to ground
|
||||
if self.horizontal_break >= self.N or self.vertical_break >= self.N:
|
||||
[self.out.connect(out_id, ConstantWireValue0()) for out_id in range(self.out.N)]
|
||||
else:
|
||||
for grounded_out_index in range(0, break_offsets):
|
||||
self.out.connect(grounded_out_index, ConstantWireValue0())
|
||||
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Reference in New Issue
Block a user