Implemented generation to flat Verilog format and improved some other minor bits of code.
This commit is contained in:
honzastor
parent
c9ddb834f7
commit
ef5dc80382
1
.gitignore
vendored
1
.gitignore
vendored
@ -3,4 +3,5 @@ __pycache__/
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test.py
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Makefile
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*.c
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*.v
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t.py
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@ -12,6 +12,7 @@ class arithmetic_circuit():
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self.components = []
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self.circuit_wires = []
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self.c_data_type = "uint64_t"
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self.N = 1
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# TODO delete?
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self.carry_out_gate = None
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@ -39,7 +40,19 @@ class arithmetic_circuit():
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def get_carry_wire(self):
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return self.out.get_wire(1)
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# FLAT C GENERATION #
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def get_circuit_wires(self):
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for component in self.components:
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if not [item for item in self.circuit_wires if item[1] == component.a.name]:
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self.circuit_wires.append((component.a, component.a.name))
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if not [item for item in self.circuit_wires if item[1] == component.b.name]:
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self.circuit_wires.append((component.b, component.b.name))
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if not [item for item in self.circuit_wires if item[1] == component.output.name]:
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self.circuit_wires.append((component.output, component.output.name))
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""" C CODE GENERATION """
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# FLAT C #
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@staticmethod
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def get_includes_c():
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return f"#include <stdio.h>\n#include <stdint.h>\n\n"
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@ -71,7 +84,7 @@ class arithmetic_circuit():
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file_object.write(f" return {self.out.prefix}"+";\n}")
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file_object.close()
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# HIERARCHICAL C GENERATION #
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# HIERARCHICAL C #
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def get_function_blocks_c(self):
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# Add unique 1-bit adder components (ha, fa)
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self.component_types = self.get_component_types()
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@ -116,6 +129,36 @@ class arithmetic_circuit():
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file_object.write(self.get_circuit_c())
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file_object.close()
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""" VERILOG CODE GENERATION """
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# FLAT VERILOG #
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def get_prototype_v(self):
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return f"module {self.prefix}(input [{self.N-1}:0] {self.a.prefix}, input [{self.N-1}:0] {self.b.prefix}, output [{self.N}:0] {self.out.prefix});\n"
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def get_declaration_v_flat(self):
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return f"".join([c.get_declaration_v_flat() for c in self.components])
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def get_init_v_flat(self, offset: int = 0, array: bool = False):
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return "".join([c.get_init_v_flat(offset=self.components.index(c), array=True) for c in self.components])
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def get_function_sum_cout_v_flat(self):
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return "".join([c.get_function_sum_cout_v_flat(offset=self.components.index(c)) for c in self.components])
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def get_function_sum_v_flat(self):
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return "".join([c.get_function_sum_v_flat(offset=self.components.index(c)) for c in self.components])
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def get_function_carry_v_flat(self):
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return f"{self.get_previous_component().get_function_carry_v_flat(offset=self.out.N-1)}"
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# Generating flat V code representation of circuit
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def get_v_code_flat(self, file_object):
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file_object.write(self.get_prototype_v())
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file_object.write(self.get_declaration_v_flat()+"\n")
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file_object.write(self.get_init_v_flat(array=False)+"\n")
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file_object.write(self.get_function_sum_v_flat())
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file_object.write(self.get_function_carry_v_flat())
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file_object.write(f"endmodule")
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file_object.close()
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class half_adder(arithmetic_circuit):
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def __init__(self, a: wire, b: wire, prefix: str = "ha"):
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@ -125,7 +168,7 @@ class half_adder(arithmetic_circuit):
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self.a = a
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self.b = b
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# 2 wires for component's bus output (sum, cout)
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self.out = bus("out", 2)
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self.out = bus("out", self.N+1)
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# Sum
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# XOR gate for calculation of 1-bit sum
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@ -139,7 +182,8 @@ class half_adder(arithmetic_circuit):
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self.add_component(obj_and_gate)
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self.out.connect(1, obj_and_gate.output)
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# FLAT C GENERATION #
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""" C CODE GENERATION """
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# FLAT C #
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# Half adder function prototype with two inputs
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def get_prototype_c(self):
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return f"{self.c_data_type} {self.prefix}({self.c_data_type} {self.a.name}, {self.c_data_type} {self.b.name})" + "{" + "\n"
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@ -147,23 +191,14 @@ class half_adder(arithmetic_circuit):
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# Obtaining list of all the unique circuit wires from all contained logic gates
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# to ensure non-recurring declaration of same wires
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def get_declaration_c_flat(self):
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for component in self.components:
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if not [item for item in self.circuit_wires if item[1] == component.a.name]:
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self.circuit_wires.append((component.a, component.a.name))
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if not [item for item in self.circuit_wires if item[1] == component.b.name]:
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self.circuit_wires.append((component.b, component.b.name))
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if not [item for item in self.circuit_wires if item[1] == component.output.name]:
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self.circuit_wires.append((component.output, component.output.name))
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self.get_circuit_wires()
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# Unique declaration of all circuit's interconnections
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return "".join([c[0].get_declaration_c() for c in self.circuit_wires])
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# Half adder wires values initialization
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def get_init_c_flat(self):
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self.a.prefix = self.a.name if self.a.prefix == "" else self.a.prefix
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self.b.prefix = self.b.name if self.b.prefix == "" else self.b.prefix
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# self.a.prefix = self.a.name if self.a.prefix == "" else self.a.prefix
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# self.b.prefix = self.b.name if self.b.prefix == "" else self.b.prefix
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return f" {self.components[0].a.name} = {self.a.get_wire_value_c(offset=self.a.index)};\n" + \
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f" {self.components[0].b.name} = {self.b.get_wire_value_c(offset=self.b.index)};\n" + \
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f" {self.components[0].output.name} = {self.components[0].get_init_c_flat()};\n" + \
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@ -175,7 +210,7 @@ class half_adder(arithmetic_circuit):
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def get_function_carry_c_flat(self, offset: int = 1):
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return f" {self.out.prefix} |= {self.components[1].output.return_wire_value_c(offset=offset)};\n"
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# HIERARCHICAL C GENERATION #
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# HIERARCHICAL C #
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def get_function_block_c(self):
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self.component_types = self.get_component_types()
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self.prefix = "ha"
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@ -208,6 +243,31 @@ class half_adder(arithmetic_circuit):
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f"{self.get_function_carry_c_hier()}" + \
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f" return {self.out.prefix}"+";\n}"
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""" VERILOG CODE GENERATION """
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# FLAT VERILOG #
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def get_prototype_v(self):
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return f"module {self.prefix}(input {self.a.name}, input {self.b.name}, output [{self.N}:0]{self.out.prefix});\n"
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def get_declaration_v_flat(self):
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self.get_circuit_wires()
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# Unique declaration of all circuit's interconnections
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return "".join([c[0].get_declaration_v() for c in self.circuit_wires])
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# Half adder wires values initialization
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def get_init_v_flat(self, offset: int = 0, array: bool = False, ):
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self.a.prefix = self.a.name if self.a.prefix == "" else self.a.prefix
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self.b.prefix = self.b.name if self.b.prefix == "" else self.b.prefix
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return f" assign {self.components[0].a.name} = {self.a.get_wire_value_v(offset=offset, array=array)};\n" + \
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f" assign {self.components[0].b.name} = {self.b.get_wire_value_v(offset=offset, array=array)};\n" + \
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f" assign {self.components[0].output.name} = {self.components[0].get_init_v_flat()};\n" + \
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f" assign {self.components[1].output.name} = {self.components[1].get_init_v_flat()};\n"
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def get_function_sum_v_flat(self, offset: int = 0):
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return f" assign {self.out.prefix}[{offset}] = {self.components[0].output.name};\n"
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def get_function_carry_v_flat(self, offset: int = 1):
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return f" assign {self.out.prefix}[{offset}] = {self.components[1].output.name};\n"
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class full_adder(arithmetic_circuit):
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def __init__(self, a: wire, b: wire, c: wire, prefix: str = "fa"):
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@ -218,7 +278,7 @@ class full_adder(arithmetic_circuit):
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self.b = b
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self.c = c
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# 2 wires for component's bus output (sum, cout)
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self.out = bus("out", 2)
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self.out = bus("out", self.N+1)
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# PG logic
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propagate_xor_gate1 = xor_gate(a, b, prefix, outid=0)
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@ -246,7 +306,8 @@ class full_adder(arithmetic_circuit):
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self.propagate = propagate_xor_gate1.output
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self.generate = generate_and_gate1.output
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# FLAT C GENERATION #
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""" C CODE GENERATION """
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# FLAT C #
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# Full adder function prototype with three inputs
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def get_prototype_c(self):
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return f"{self.c_data_type} {self.prefix}({self.c_data_type} {self.a.name}, {self.c_data_type} {self.b.name}, {self.c_data_type} {self.c.name})" + "{" + "\n"
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@ -254,16 +315,7 @@ class full_adder(arithmetic_circuit):
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# Obtaining list of all the unique circuit wires from all contained logic gates
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# to ensure non-recurring declaration of same wires
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def get_declaration_c_flat(self):
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for component in self.components:
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if not [item for item in self.circuit_wires if item[1] == component.a.name]:
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self.circuit_wires.append((component.a, component.a.name))
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if not [item for item in self.circuit_wires if item[1] == component.b.name]:
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self.circuit_wires.append((component.b, component.b.name))
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if not [item for item in self.circuit_wires if item[1] == component.output.name]:
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self.circuit_wires.append((component.output, component.output.name))
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self.get_circuit_wires()
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# Unique declaration of all circuit's interconnections
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return "".join([c[0].get_declaration_c() for c in self.circuit_wires])
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@ -287,7 +339,7 @@ class full_adder(arithmetic_circuit):
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def get_function_carry_c_flat(self, offset: int = 1):
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return f" {self.out.prefix} |= {self.components[4].output.return_wire_value_c(offset=offset)};\n"
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# HIERARCHICAL C GENERATION #
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# HIERARCHICAL C #
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def get_function_block_c(self):
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self.component_types = self.get_component_types()
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self.prefix = "fa"
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@ -340,6 +392,36 @@ class full_adder(arithmetic_circuit):
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f"{self.get_function_carry_c_hier()}" + \
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f" return {self.out.prefix}"+";\n}"
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""" VERILOG CODE GENERATION """
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# FLAT VERILOG #
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def get_prototype_v(self):
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return f"module {self.prefix}(input {self.a.name}, input {self.b.name}, input {self.c.name}, output [{self.N}:0]{self.out.prefix});\n"
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def get_declaration_v_flat(self):
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self.get_circuit_wires()
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# Unique declaration of all circuit's interconnections
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return "".join([c[0].get_declaration_v() for c in self.circuit_wires])
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# Full adder wires values initialization
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def get_init_v_flat(self, offset: int = 0, array: bool = False):
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self.a.prefix = self.a.name if self.a.prefix == "" else self.a.prefix
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self.b.prefix = self.b.name if self.b.prefix == "" else self.b.prefix
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self.c.prefix = self.c.name
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return f" assign {self.components[0].a.name} = {self.a.get_wire_value_v(offset=offset, array=array)};\n" + \
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f" assign {self.components[0].b.name} = {self.b.get_wire_value_v(offset=offset, array=array)};\n" + \
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f" assign {self.components[2].b.name} = {self.c.get_wire_value_v(offset=offset, array=array)};\n" + \
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f" assign {self.components[0].output.name} = {self.components[0].get_init_v_flat()};\n" + \
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f" assign {self.components[1].output.name} = {self.components[1].get_init_v_flat()};\n" + \
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f" assign {self.components[2].output.name} = {self.components[2].get_init_v_flat()};\n" + \
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f" assign {self.components[3].output.name} = {self.components[3].get_init_v_flat()};\n" + \
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f" assign {self.components[4].output.name} = {self.components[4].get_init_v_flat()};\n"
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def get_function_sum_v_flat(self, offset: int = 0):
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return f" assign {self.out.prefix}[{offset}] = {self.components[2].output.name};\n"
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def get_function_carry_v_flat(self, offset: int = 1):
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return f" assign {self.out.prefix}[{offset}] = {self.components[4].output.name};\n"
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class signed_ripple_carry_adder(arithmetic_circuit):
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def __init__(self, a: bus, b: bus, prefix: str = "s_rca"):
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@ -381,7 +463,8 @@ class signed_ripple_carry_adder(arithmetic_circuit):
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self.add_component(sign_xor_1)
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self.add_component(sign_xor_2)
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# FLAT C GENERATION #
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""" VERILOG CODE GENERATION """
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# FLAT C #
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# Initialization of 1-bit adders and sign extension XOR gates
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def get_init_c_flat(self):
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self.components[-2].output.prefix = self.components[-2].output.name
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@ -400,7 +483,7 @@ class signed_ripple_carry_adder(arithmetic_circuit):
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def get_function_carry_c_flat(self):
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return f" {self.out.prefix} |= {self.get_previous_component().output.return_wire_value_c(offset = self.N)};\n"
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# HIERARCHICAL C GENERATION #
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# HIERARCHICAL C #
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def get_declaration_c_hier(self):
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self.cout = bus(N=self.N, prefix="cout")
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return "".join(self.a.get_wire_declaration_c()) + \
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@ -418,6 +501,26 @@ class signed_ripple_carry_adder(arithmetic_circuit):
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def get_function_carry_c_hier(self):
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return f" {self.out.prefix} |= {self.get_previous_component().get_gate_output_c(a=self.components[-2].output, b=self.cout.bus[-1], offset=self.out.N-1)};\n"
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""" VERILOG CODE GENERATION """
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# FLAT C #
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# Initialization of 1-bit adders and sign extension XOR gates
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def get_init_v_flat(self, offset: int = 0, array: bool = False):
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self.components[-2].output.prefix = self.components[-2].output.name
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self.components[-3].get_carry_wire().prefix = self.components[-3].get_carry_wire().name
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return f"".join([c.get_init_v_flat(offset=self.components.index(c), array=True) for c in self.components[:-2]]) + \
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f" assign {self.components[-2].a.name} = {self.a.get_wire_value_v(offset=self.N-1, array=True)};\n" + \
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f" assign {self.components[-2].b.name} = {self.b.get_wire_value_v(offset=self.N-1, array=True)};\n" + \
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f" assign {self.components[-2].output.name} = {self.components[-2].get_init_v_flat()};\n" + \
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f" assign {self.components[-1].a.name} = {self.components[-2].output.get_wire_value_v(offset=offset, array=array)};\n" + \
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f" assign {self.components[-1].b.name} = {self.components[-3].get_carry_wire().get_wire_value_v()};\n" + \
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f" assign {self.components[-1].output.name} = {self.components[-1].get_init_v_flat()};\n"
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def get_function_sum_v_flat(self, offset: int = 0):
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return "".join([c.get_function_sum_v_flat(offset=self.components.index(c)) for c in self.components[:-2]])
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def get_function_carry_v_flat(self):
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return f" assign {self.out.prefix}[{self.N}] = {self.get_previous_component().output.return_wire_value_v(offset=self.N)};\n"
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class unsigned_ripple_carry_adder(arithmetic_circuit):
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def __init__(self, a: bus, b: bus, prefix: str = "u_rca"):
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@ -456,14 +559,22 @@ class unsigned_ripple_carry_adder(arithmetic_circuit):
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if __name__ == "__main__":
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a = bus(N=8, prefix="a")
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b = bus(N=8, prefix="b")
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rca = unsigned_ripple_carry_adder(a, b)
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# rca.get_c_code_hier(open("h_u_rca8.c", "w"))
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rca = unsigned_ripple_carry_adder(a, b, prefix="u_rca8")
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# rca.get_c_code_hier(open("h_u_rca4.c", "w"))
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# rca.get_c_code_flat(open("f_u_rca8.c", "w"))
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rca.get_v_code_flat(open("f_u_rca8.v", "w"))
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w1 = wire(name="a")
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w2 = wire(name="b")
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w3 = wire(name="cout")
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fa = full_adder(w1, w2, w3, prefix="h_fa")
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ha = half_adder(w1, w2, prefix="h_ha")
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fa = full_adder(w1, w2, w3, prefix="f_fa")
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ha = half_adder(w1, w2, prefix="f_ha")
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# ha.get_c_code_hier(open("h_ha.c","w"))
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# ha.get_c_code_flat(open("f_ha.c","w"))
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# ha.get_v_code_flat(open("f_ha.v","w"))
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# fa.get_c_code_flat(open("f_fa.c","w"))
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# fa.get_v_code_flat(open("f_fa.v","w"))
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gate = not_gate(w1)
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# gate.get_c_code(open("not_gate.c","w"))
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# gate.get_v_code(open("not_gate.v","w"))
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@ -5,7 +5,7 @@ from wire_components import wire
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class logic_gate():
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def __init__(self, a: wire, b: wire, prefix: str = "w"):
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def __init__(self, a: wire, b: wire, prefix: str = "gate"):
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self.a = wire(name=prefix+"_"+a.name.replace(prefix+"_", ""), value=a.value)
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self.b = wire(name=prefix+"_"+b.name.replace(prefix+"_", ""), value=b.value)
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self.prefix = prefix
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@ -13,15 +13,19 @@ class logic_gate():
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def get_component_types(self):
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return list([self])
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|
||||
# FLAT C GENERATION #
|
||||
""" C CODE GENERATION """
|
||||
# FLAT C #
|
||||
@staticmethod
|
||||
def get_includes_c():
|
||||
return f"#include <stdio.h>\n#include <stdint.h>\n\n"
|
||||
|
||||
def get_prototype_c(self):
|
||||
self.a.name = self.a.name.replace(self.prefix+"_", "")
|
||||
self.b.name = self.b.name.replace(self.prefix+"_", "")
|
||||
return f"uint8_t {self.gate_type}(uint8_t {self.a.name}, uint8_t {self.b.name})" + "{" + "\n"
|
||||
self.a.name = self.a.name.replace(self.prefix, "", 1)
|
||||
self.b.name = self.b.name.replace(self.prefix, "", 1)
|
||||
return f"uint8_t {self.prefix}_{self.gate_type}(uint8_t {self.a.name}, uint8_t {self.b.name})" + "{" + "\n"
|
||||
|
||||
def get_function_c(self):
|
||||
return f"{self.a.get_wire_value_c()} {self.operator} {self.b.get_wire_value_c()}"
|
||||
|
||||
def get_declaration_c_flat(self):
|
||||
return f"{self.a.get_declaration_c()}{self.b.get_declaration_c()}{self.output.get_declaration_c()}"
|
||||
@ -29,12 +33,7 @@ class logic_gate():
|
||||
def get_init_c_flat(self):
|
||||
return f"{self.a.name} {self.operator} {self.b.name}"
|
||||
|
||||
def get_function_c(self):
|
||||
self.a.prefix = self.a.name.replace(self.prefix+"_", "")
|
||||
self.b.prefix = self.b.name.replace(self.prefix+"_", "")
|
||||
return f"{self.a.get_wire_value_c()} {self.operator} {self.b.get_wire_value_c()}"
|
||||
|
||||
# Generating flat C code representation of separate logic gate
|
||||
# Generating flat C code representation of the logic gate itself
|
||||
# (i.e. not as a component of bigger circuit)
|
||||
def get_c_code(self, file_object):
|
||||
file_object.write(self.get_includes_c())
|
||||
@ -55,13 +54,38 @@ class logic_gate():
|
||||
def get_gate_output_c(self, a: wire, b: wire, offset: int = 0):
|
||||
return f"({self.gate_type}({a.name}, {b.name}) & 0x01) << {offset}"
|
||||
|
||||
""" VERILOG CODE GENERATION """
|
||||
# FLAT VERILOG #
|
||||
def get_prototype_v(self):
|
||||
self.a.name = self.a.name.replace(self.prefix, "", 1)
|
||||
self.b.name = self.b.name.replace(self.prefix, "", 1)
|
||||
self.output.name = self.output.name.replace(self.prefix, "", 1)
|
||||
return f"module {self.prefix}_{self.gate_type}(input {self.a.name}, input {self.b.name}, output {self.output.name});\n"
|
||||
|
||||
def get_declaration_v_flat(self):
|
||||
return f"{self.a.get_declaration_v()}{self.b.get_declaration_v()}{self.output.get_declaration_v()}"
|
||||
|
||||
def get_function_v(self):
|
||||
return f"{self.a.name} {self.operator} {self.b.name}"
|
||||
|
||||
def get_init_v_flat(self):
|
||||
return f"{self.a.name} {self.operator} {self.b.name}"
|
||||
|
||||
# Generating flat Verilog code representation of the logic gate itself
|
||||
# (i.e. not as a component of bigger circuit)
|
||||
def get_v_code(self, file_object):
|
||||
file_object.write(self.get_prototype_v())
|
||||
file_object.write(f" assign {self.output.name} = {self.get_function_v()};\n")
|
||||
file_object.write(f"endmodule")
|
||||
file_object.close()
|
||||
|
||||
|
||||
# Single-input
|
||||
class not_gate(logic_gate):
|
||||
def __init__(self, a: wire, prefix: str = "w", outid: int = 0):
|
||||
def __init__(self, a: wire, prefix: str = "", outid: int = 0):
|
||||
self.gate_type = "not_gate"
|
||||
self.operator = "~"
|
||||
self.a = wire(prefix+"_"+a.name.replace(prefix+"_", ""), a.value)
|
||||
self.a = wire(name=prefix+"_"+a.name.replace(prefix+"_", ""), value=a.value)
|
||||
self.prefix = prefix
|
||||
|
||||
if self.a.value == 1:
|
||||
@ -69,9 +93,14 @@ class not_gate(logic_gate):
|
||||
else:
|
||||
self.output = wire(name=prefix+"_y"+str(outid), value=1)
|
||||
|
||||
# FLAT C GENERATION #
|
||||
""" C CODE GENERATION """
|
||||
# FLAT C #
|
||||
def get_prototype_c(self):
|
||||
return f"uint8_t {self.gate_type}(uint8_t a)" + "{" + "\n"
|
||||
self.a.name = self.a.name.replace(self.prefix, "", 1)
|
||||
return f"uint8_t {self.prefix}_{self.gate_type}(uint8_t {self.a.name})" + "{" + "\n"
|
||||
|
||||
def get_function_c(self):
|
||||
return f"{self.operator}{self.a.get_wire_value_c()} & 0x01 << 0"
|
||||
|
||||
def get_declaration_c(self):
|
||||
return f"{self.a.get_declaration_c()}{self.output.get_declaration_c()}"
|
||||
@ -79,11 +108,7 @@ class not_gate(logic_gate):
|
||||
def get_init_c_flat(self):
|
||||
return f"{self.operator}{self.a.name}"
|
||||
|
||||
def get_function_c(self):
|
||||
self.a.prefix = self.a.name.replace(self.prefix+"_", "")
|
||||
return f"{self.operator}{self.a.get_wire_value_c()} & 0x01 << 0"
|
||||
|
||||
# HIERARCHICAL C GENERATION #
|
||||
# HIERARCHICAL C #
|
||||
def get_function_block_c(self):
|
||||
self.a.name = "a"
|
||||
return f"{self.get_prototype_c()}" + \
|
||||
@ -95,10 +120,27 @@ class not_gate(logic_gate):
|
||||
def get_gate_output_c(self, a: wire, offset: int = 0):
|
||||
return f"({self.gate_type}({a.name}) & 0x01) << {offset}"
|
||||
|
||||
""" VERILOG CODE GENERATION """
|
||||
# FLAT VERILOG #
|
||||
def get_prototype_v(self):
|
||||
self.a.name = self.a.name.replace(self.prefix, "", 1)
|
||||
self.output.name = self.output.name.replace(self.prefix, "", 1)
|
||||
return f"module {self.prefix}_{self.gate_type}(input {self.a.name}, output {self.output.name});\n"
|
||||
|
||||
def get_declaration_v_flat(self):
|
||||
return f"{self.a.get_declaration_v()}{self.output.get_declaration_v()}"
|
||||
|
||||
def get_function_v(self):
|
||||
# self.a.name = self.a.name.replace(self.prefix+"_", "")
|
||||
return f" {self.operator}{self.a.name}"
|
||||
|
||||
def get_init_v_flat(self):
|
||||
return f"{self.a.name} {self.operator} {self.b.name}"
|
||||
|
||||
|
||||
# Two-input
|
||||
class and_gate(logic_gate):
|
||||
def __init__(self, a: wire, b: wire, prefix: str = "w", outid: int = 0):
|
||||
def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
|
||||
super().__init__(a, b, prefix)
|
||||
self.gate_type = "and_gate"
|
||||
self.operator = "&"
|
||||
@ -110,7 +152,7 @@ class and_gate(logic_gate):
|
||||
|
||||
|
||||
class nand_gate(logic_gate):
|
||||
def __init__(self, a: wire, b: wire, prefix: str = "w", outid: int = 0):
|
||||
def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
|
||||
super().__init__(a, b, prefix)
|
||||
self.gate_type = "nand_gate"
|
||||
self.operator = "&"
|
||||
@ -120,12 +162,17 @@ class nand_gate(logic_gate):
|
||||
else:
|
||||
self.output = wire(name=prefix+"_y"+str(outid), value=1)
|
||||
|
||||
""" C CODE GENERATION """
|
||||
def get_function_c(self):
|
||||
return "~("+(super().get_function_c())+f") & 0x01 << 0"
|
||||
|
||||
""" VERILOG CODE GENERATION """
|
||||
def get_function_v(self):
|
||||
return "~("+(super().get_function_v())+f")"
|
||||
|
||||
|
||||
class or_gate(logic_gate):
|
||||
def __init__(self, a: wire, b: wire, prefix: str = "w", outid: int = 0):
|
||||
def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
|
||||
super().__init__(a, b, prefix)
|
||||
self.gate_type = "or_gate"
|
||||
self.operator = "|"
|
||||
@ -137,7 +184,7 @@ class or_gate(logic_gate):
|
||||
|
||||
|
||||
class nor_gate(logic_gate):
|
||||
def __init__(self, a: wire, b: wire, prefix: str = "w", outid: int = 0):
|
||||
def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
|
||||
super().__init__(a, b, prefix)
|
||||
self.gate_type = "nor_gate"
|
||||
self.operator = "|"
|
||||
@ -147,12 +194,17 @@ class nor_gate(logic_gate):
|
||||
else:
|
||||
self.output = wire(name=prefix+"_y"+str(outid), value=1)
|
||||
|
||||
""" C CODE GENERATION """
|
||||
def get_function_c(self):
|
||||
return "~("+(super().get_function_c())+") & 0x01 << 0"
|
||||
|
||||
""" VERILOG CODE GENERATION """
|
||||
def get_function_v(self):
|
||||
return "~("+(super().get_function_v())+f")"
|
||||
|
||||
|
||||
class xor_gate(logic_gate):
|
||||
def __init__(self, a: wire, b: wire, prefix: str = "w", outid: int = 0):
|
||||
def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
|
||||
super().__init__(a, b, prefix)
|
||||
self.gate_type = "xor_gate"
|
||||
self.operator = "^"
|
||||
@ -164,7 +216,7 @@ class xor_gate(logic_gate):
|
||||
|
||||
|
||||
class xnor_gate(logic_gate):
|
||||
def __init__(self, a: wire, b: wire, prefix: str = "w", outid: int = 0):
|
||||
def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
|
||||
super().__init__(a, b, prefix)
|
||||
self.gate_type = "xnor_gate"
|
||||
self.operator = "^"
|
||||
@ -174,5 +226,10 @@ class xnor_gate(logic_gate):
|
||||
else:
|
||||
self.output = wire(name=prefix+"_y"+str(outid), value=1)
|
||||
|
||||
""" C CODE GENERATION """
|
||||
def get_function_c(self):
|
||||
return "~("+(super().get_function_c())+") & 0x01 << 0"
|
||||
|
||||
""" VERILOG CODE GENERATION """
|
||||
def get_function_v(self):
|
||||
return "~("+(super().get_function_v())+f")"
|
||||
|
||||
@ -8,16 +8,31 @@ class wire():
|
||||
self.value = value
|
||||
self.index = index
|
||||
|
||||
# C GENERATION #
|
||||
# C CODE GENERATION #
|
||||
def get_declaration_c(self):
|
||||
return f" uint8_t {self.name} = 0;\n"
|
||||
|
||||
def get_wire_value_c(self, offset: int = 0):
|
||||
return f"(({self.prefix} >> {offset}) & 0x01)"
|
||||
name = self.name if self.prefix == "" else self.prefix
|
||||
return f"(({name} >> {offset}) & 0x01)"
|
||||
|
||||
def return_wire_value_c(self, offset: int = 0):
|
||||
return f"({self.name} & 0x01) << {offset}"
|
||||
|
||||
# VERILOG CODE GENERATION #
|
||||
def get_declaration_v(self):
|
||||
return f" wire {self.name};\n"
|
||||
|
||||
def get_wire_value_v(self, offset: int = 0, array: bool = False):
|
||||
name = self.name if self.prefix == "" else self.prefix
|
||||
if array is True:
|
||||
return f"{name}[{offset}]"
|
||||
else:
|
||||
return f"{name}"
|
||||
|
||||
def return_wire_value_v(self, offset: int = 0):
|
||||
return f"{self.name}"
|
||||
|
||||
|
||||
class bus():
|
||||
def __init__(self, prefix: str = "bus", N: int = 1):
|
||||
@ -40,7 +55,7 @@ class bus():
|
||||
self.bus = [wire(name=prefix+"_"+str(i), index=i) for i in range(N)]
|
||||
self.N = N
|
||||
|
||||
# C GENERATION #
|
||||
# C CODE GENERATION #
|
||||
def get_wire_value_c(self, offset: int = 0):
|
||||
return self.bus[offset].get_wire_value_c(offset=offset)
|
||||
|
||||
@ -55,3 +70,7 @@ class bus():
|
||||
return f" uint64_t {self.prefix} = 0;\n"
|
||||
else:
|
||||
return f" uint8_t {self.prefix} = 0;\n"
|
||||
|
||||
# VERILOG CODE GENERATION #
|
||||
def get_wire_value_v(self, offset: int = 0, array: bool = False):
|
||||
return self.bus[offset].get_wire_value_v(offset=offset, array=array)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user