Delete logic_gates_generator.py
Outdated file, replaced by logic_gates.py
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Jan Klhůfek
GitHub
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from wire_components import wire
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""" LOGIC GATE COMPONENTS """
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class logic_gate():
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def __init__(self, a: wire, b: wire, prefix: str = "gate"):
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self.a = wire(name=prefix+"_"+a.name.replace(prefix+"_", ""), value=a.value)
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self.b = wire(name=prefix+"_"+b.name.replace(prefix+"_", ""), value=b.value)
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self.prefix = prefix
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def get_component_types(self):
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return list([self])
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""" C CODE GENERATION """
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# FLAT C #
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@staticmethod
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def get_includes_c():
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return f"#include <stdio.h>\n#include <stdint.h>\n\n"
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def get_prototype_c(self):
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self.a.name = self.a.name.replace(self.prefix, "", 1)
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self.b.name = self.b.name.replace(self.prefix, "", 1)
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return f"uint8_t {self.prefix}_{self.gate_type}(uint8_t {self.a.name}, uint8_t {self.b.name})" + "{" + "\n"
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def get_function_c(self):
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return f"{self.a.get_wire_value_c()} {self.operator} {self.b.get_wire_value_c()}"
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def get_declaration_c_flat(self):
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return f"{self.a.get_declaration_c()}{self.b.get_declaration_c()}{self.output.get_declaration_c()}"
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def get_init_c_flat(self):
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return f"{self.a.name} {self.operator} {self.b.name}"
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# Generating flat C code representation of the logic gate itself
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# (i.e. not as a component of bigger circuit)
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def get_c_code(self, file_object):
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file_object.write(self.get_includes_c())
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file_object.write(self.get_prototype_c())
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file_object.write(" return "+(self.get_function_c())+";\n}")
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file_object.close()
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# HIERARCHICAL C GENERATION #
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def get_function_block_c(self):
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self.a.name = "a"
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self.b.name = "b"
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return f"{self.get_prototype_c()}" + \
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f" return "+(self.get_function_c())+";\n}\n\n"
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def get_invocation_c(self, a: wire, b: wire):
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return f"{self.gate_type}({a.name}, {b.name});"
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def get_gate_output_c(self, a: wire, b: wire, offset: int = 0):
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return f"({self.gate_type}({a.name}, {b.name}) & 0x01) << {offset}"
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""" VERILOG CODE GENERATION """
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# FLAT VERILOG #
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def get_prototype_v(self):
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self.a.name = self.a.name.replace(self.prefix, "", 1)
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self.b.name = self.b.name.replace(self.prefix, "", 1)
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self.output.name = self.output.name.replace(self.prefix, "", 1)
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return f"module {self.prefix}_{self.gate_type}(input {self.a.name}, input {self.b.name}, output {self.output.name});\n"
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def get_declaration_v_flat(self):
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return f"{self.a.get_declaration_v()}{self.b.get_declaration_v()}{self.output.get_declaration_v()}"
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def get_function_v(self):
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return f"{self.a.name} {self.operator} {self.b.name}"
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def get_init_v_flat(self):
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return f"{self.a.name} {self.operator} {self.b.name}"
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# Generating flat Verilog code representation of the logic gate itself
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# (i.e. not as a component of bigger circuit)
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def get_v_code(self, file_object):
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file_object.write(self.get_prototype_v())
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file_object.write(f" assign {self.output.name} = {self.get_function_v()};\n")
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file_object.write(f"endmodule")
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file_object.close()
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# Single-input
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class not_gate(logic_gate):
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def __init__(self, a: wire, prefix: str = "", outid: int = 0):
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self.gate_type = "not_gate"
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self.operator = "~"
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self.a = wire(name=prefix+"_"+a.name.replace(prefix+"_", ""), value=a.value)
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self.prefix = prefix
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if self.a.value == 1:
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self.output = wire(name=prefix+"_y"+str(outid), value=0)
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else:
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self.output = wire(name=prefix+"_y"+str(outid), value=1)
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""" C CODE GENERATION """
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# FLAT C #
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def get_prototype_c(self):
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self.a.name = self.a.name.replace(self.prefix, "", 1)
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return f"uint8_t {self.prefix}_{self.gate_type}(uint8_t {self.a.name})" + "{" + "\n"
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def get_function_c(self):
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return f"{self.operator}{self.a.get_wire_value_c()} & 0x01 << 0"
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def get_declaration_c(self):
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return f"{self.a.get_declaration_c()}{self.output.get_declaration_c()}"
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def get_init_c_flat(self):
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return f"{self.operator}{self.a.name}"
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# HIERARCHICAL C #
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def get_function_block_c(self):
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self.a.name = "a"
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return f"{self.get_prototype_c()}" + \
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f" return "+(self.get_function_c())+";\n}\n\n"
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def get_invocation_c(self, a: wire):
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return f"{self.gate_type}({a.name});"
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def get_gate_output_c(self, a: wire, offset: int = 0):
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return f"({self.gate_type}({a.name}) & 0x01) << {offset}"
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""" VERILOG CODE GENERATION """
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# FLAT VERILOG #
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def get_prototype_v(self):
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self.a.name = self.a.name.replace(self.prefix, "", 1)
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self.output.name = self.output.name.replace(self.prefix, "", 1)
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return f"module {self.prefix}_{self.gate_type}(input {self.a.name}, output {self.output.name});\n"
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def get_declaration_v_flat(self):
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return f"{self.a.get_declaration_v()}{self.output.get_declaration_v()}"
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def get_function_v(self):
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# self.a.name = self.a.name.replace(self.prefix+"_", "")
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return f" {self.operator}{self.a.name}"
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def get_init_v_flat(self):
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return f"{self.a.name} {self.operator} {self.b.name}"
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# Two-input
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class and_gate(logic_gate):
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def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
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super().__init__(a, b, prefix)
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self.gate_type = "and_gate"
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self.operator = "&"
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if a.value == 1 and b.value == 1:
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self.output = wire(name=prefix+"_y"+str(outid), value=1)
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else:
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self.output = wire(name=prefix+"_y"+str(outid), value=0)
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class nand_gate(logic_gate):
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def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
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super().__init__(a, b, prefix)
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self.gate_type = "nand_gate"
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self.operator = "&"
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if (self.a.value == 1 and self.b.value == 1):
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self.output = wire(name=prefix+"_y"+str(outid), value=0)
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else:
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self.output = wire(name=prefix+"_y"+str(outid), value=1)
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""" C CODE GENERATION """
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def get_function_c(self):
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return "~("+(super().get_function_c())+f") & 0x01 << 0"
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""" VERILOG CODE GENERATION """
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def get_function_v(self):
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return "~("+(super().get_function_v())+f")"
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class or_gate(logic_gate):
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def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
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super().__init__(a, b, prefix)
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self.gate_type = "or_gate"
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self.operator = "|"
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if self.a.value == 1 or self.b.value == 1:
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self.output = wire(name=prefix+"_y"+str(outid), value=1)
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else:
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self.output = wire(name=prefix+"_y"+str(outid), value=0)
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class nor_gate(logic_gate):
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def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
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super().__init__(a, b, prefix)
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self.gate_type = "nor_gate"
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self.operator = "|"
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if self.a.value == 1 or self.b.value == 1:
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self.output = wire(name=prefix+"_y"+str(outid), value=0)
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else:
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self.output = wire(name=prefix+"_y"+str(outid), value=1)
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""" C CODE GENERATION """
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def get_function_c(self):
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return "~("+(super().get_function_c())+") & 0x01 << 0"
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""" VERILOG CODE GENERATION """
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def get_function_v(self):
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return "~("+(super().get_function_v())+f")"
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class xor_gate(logic_gate):
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def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
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super().__init__(a, b, prefix)
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self.gate_type = "xor_gate"
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self.operator = "^"
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if (a.value == 1 and b.value == 0) or (a.value == 0 and b.value == 1):
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self.output = wire(name=prefix+"_y"+str(outid), value=1)
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else:
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self.output = wire(name=prefix+"_y"+str(outid), value=0)
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class xnor_gate(logic_gate):
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def __init__(self, a: wire, b: wire, prefix: str = "", outid: int = 0):
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super().__init__(a, b, prefix)
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self.gate_type = "xnor_gate"
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self.operator = "^"
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if (self.a.value == 1 and self.b.value == 0) or (self.a.value == 0 and self.b.value == 1):
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self.output = wire(name=prefix+"_y"+str(outid), value=0)
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else:
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self.output = wire(name=prefix+"_y"+str(outid), value=1)
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""" C CODE GENERATION """
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def get_function_c(self):
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return "~("+(super().get_function_c())+") & 0x01 << 0"
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""" VERILOG CODE GENERATION """
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def get_function_v(self):
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return "~("+(super().get_function_v())+f")"
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