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# ArithsGen – tool for arithmetic circuits generation
# ArithsGenMig – tool for arithmetic circuits generation on MIG backend
[![made-with-python](https://img.shields.io/badge/Made%20with-Python-1f425f.svg)](https://www.python.org/)
[![Documentation](https://img.shields.io/badge/api-reference-blue.svg)](https://ehw-fit.github.io/ariths-gen)
[![arXiv](https://img.shields.io/badge/arXiv-2203.04649-b31b1b.svg)](https://arxiv.org/abs/2203.04649)
## Description
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}
```
## Prebuild circuits
To enable fast work with the circuits, we published pre-build arithmetic circuits in various formats in [generated_circuits](generated_circuits) folder and as a [Release](https://github.com/ehw-fit/ariths-gen/releases).
### Usage
```bash
python3 generate_test.py
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The automatically generated documentation is available at
https://ehw-fit.github.io/ariths-gen/ .
## Supporting various PDK kits
When one uses a specific process design kit (PDK), it is not effective to implement half- and full-adders using two-inputs logic gates. These circuits are directly implemented as CMOS modules and are more effective than heuristic optimization by synthesis tool. If you want to use for example FreePDK45 library, you can call a following function before verilog code generating.
```py
from ariths_gen import set_pdk45_library
set_pdk45_library()
```
You can add a support of arbitrary PDK (see an [example](ariths_gen/pdk.py) ).
## Approximate circuits
Besides the accurate arithmetic circuits you can generate some approximate circuits. Currently we support _Broken Array Multiplier_ and _Truncated Multiplier_ both with fully connected architectures composed from half/full adders as well as faster implementations using carry save multiplier. For more details please follow files in folder [approximate_multipliers](ariths_gen/multi_bit_circuits/approximate_multipliers/). You can simply run
```bash
python3 generate_axmuls.py
```
to get the approximate circuits.
The module also supports evaluation of the proposed circuits. You can call the instation as a function (even with numpy-array input) to obtain the results of multiplication operation.
```py
from ariths_gen.wire_components.buses import Bus
from ariths_gen.multi_bit_circuits.approximate_multipliers import UnsignedBrokenArrayMultiplier
a = Bus(N=8, prefix="a_bus")
b = Bus(N=8, prefix="b_bus")
# Create BAM
bam = UnsignedBrokenArrayMultiplier(a, b, horizontal_cut=4, vertical_cut=4)
print("43 * 84 = ", bam(43, 84), " expected: ", 43 * 84)
# 43 * 84 = 3440 expected: 3612
```
for all of the possible combinations.
```py
# Evaluate all using b'casting
import numpy as np
import matplotlib.pyplot as plt
va = np.arange(256).reshape(1, -1)
vb = va.reshape(-1, 1)
r = bam(va, vb)
cax = plt.imshow(np.abs(r - (va * vb)))
plt.colorbar(cax)
plt.title("Absolute difference")
plt.xlabel("a")
plt.ylabel("b")
print("Mean average error", np.abs(r - (va * vb)).mean())
# Mean average error 956.25
```
![bam (v=4,h=4)](bam.png)
## Formal verification
The `yosys_equiv_check.sh` script enables to formally check the equivalence of generated Verilog and BLIF representations of the same circuit.
It uses the Yosys Open SYnthesis Suite tool by Claire Xenia Wolf. For further information, please visit: https://yosyshq.readthedocs.io/projects/yosys/en/latest/index.html.
## Install Yosys
```bash
sudo apt-get install yosys
```
## Execute permission
```bash
chmod +x yosys_equiv_check.sh
```
### Usage
```bash
./yosys_equiv_check.sh -v "verilog_file" -b "blif_file" -m "method" [-H]
```
For more detailed description of script's usage, use help.
```bash
./yosys_equiv_check.sh -h|--help
```
## CGP testing
The `chr2c.py` script converts the input CGP chromosome generated by ArithsGen to the corresponding C code and prints it to standard output.