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Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.

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This commit is contained in:
Honza 2022-04-17 13:04:17 +02:00
parent 9e186d10ed
commit c0dcf42499
16 changed files with 1170 additions and 796 deletions
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6
ariths_gen/core/arithmetic_circuits/general_circuit.py
View File

@ -287,7 +287,7 @@ class GeneralCircuit():
#file_object.write(self.get_declaration_python_flat()+"\n")
file_object.write(self.get_init_python_flat()+"\n")
file_object.write(self.get_function_out_python_flat())
file_object.write(self.out.return_bus_wires_sign_extend_python())
file_object.write(self.out.return_bus_wires_sign_extend_python_flat())
file_object.write(f" return {self.out.prefix}"+"\n")
""" C CODE GENERATION """
@ -346,7 +346,7 @@ class GeneralCircuit():
file_object.write(self.get_declaration_c_flat()+"\n")
file_object.write(self.get_init_c_flat()+"\n")
file_object.write(self.get_function_out_c_flat())
file_object.write(self.out.return_bus_wires_sign_extend_c())
file_object.write(self.out.return_bus_wires_sign_extend_c_flat())
file_object.write(f" return {self.out.prefix}"+";\n}")
# HIERARCHICAL C #
@ -436,7 +436,7 @@ class GeneralCircuit():
f"{self.get_declarations_c_hier()}\n" + \
f"{self.get_init_c_hier()}\n" + \
f"{self.get_function_out_c_hier()}" + \
f"{self.out.return_bus_wires_sign_extend_c()}" + \
f"{self.out.return_bus_wires_sign_extend_c_hier()}" + \
f" return {self.out.prefix}"+";\n}"
# Generating hierarchical C code representation of circuit

4
ariths_gen/core/arithmetic_circuits/multiplier_circuit.py
View File

@ -32,9 +32,9 @@ class MultiplierCircuit(ArithmeticCircuit):
def __init__(self, a, b, prefix: str, name: str, out_N: int, **kwargs):
super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=out_N, **kwargs)
# Array multipliers
# Array/approximate multipliers
def get_previous_partial_product(self, a_index: int, b_index: int, mult_type=""):
"""Used in array multipliers to get previous row's component output wires for further connection to another component's input.
"""Used in array and approximate multipliers to get previous row's component output wires for further connection to another component's input.
Args:
a_index (int): First input wire index.

0
ariths_gen/multi_bit_circuits/cgp_circuit.py → ariths_gen/core/cgp_circuit.py
View File

16
ariths_gen/multi_bit_circuits/approximate_multipliers/__init__.py
View File

@ -1,9 +1,15 @@
from ariths_gen.multi_bit_circuits.approximate_multipliers.truncated_multiplier import (
UnsignedTruncatedMultiplier,
SignedTruncatedMultiplier
from ariths_gen.multi_bit_circuits.approximate_multipliers.truncated_array_multiplier import (
UnsignedTruncatedArrayMultiplier
)
from ariths_gen.multi_bit_circuits.approximate_multipliers.broken_array_multiplier import (
UnsignedBrokenArrayMultiplier,
SignedBrokenArrayMultiplier
UnsignedBrokenArrayMultiplier
)
from ariths_gen.multi_bit_circuits.approximate_multipliers.broken_carry_save_multiplier import (
UnsignedBrokenCarrySaveMultiplier
)
from ariths_gen.multi_bit_circuits.approximate_multipliers.truncated_carry_save_multiplier import (
UnsignedTruncatedCarrySaveMultiplier
)

181
ariths_gen/multi_bit_circuits/approximate_multipliers/broken_array_multiplier.py
View File

@ -22,7 +22,7 @@ from ariths_gen.one_bit_circuits.logic_gates import (
XnorGate,
NotGate
)
from ariths_gen.multi_bit_circuits.multipliers import(
from ariths_gen.multi_bit_circuits.multipliers import (
UnsignedArrayMultiplier,
SignedArrayMultiplier
)
@ -36,7 +36,7 @@ class UnsignedBrokenArrayMultiplier(MultiplierCircuit):
stage cells by the specified horizontal and vertical cut levels.
The design promises better area and power parameters in exchange for the loss of computation precision.
The BAM design allows to save more partial product stage adders than truncated multiplier.
The BAM design allows to save more partial product stage adders than truncated multiplier architectures.
```
VERTICAL CUT=4
@ -45,25 +45,25 @@ class UnsignedBrokenArrayMultiplier(MultiplierCircuit):
│ ┌───┐ ┌───┐ ┌───┐ ┌───┐
│AND│ │AND│ │AND│ │AND│
│ └───┘ └───┘ └───┘ └───┘
│
A3B1 A2B1 A1B1 A0B1
│ ┌───┐ ┌───┐ ┌───┐ ┌───┐
│AND│ │AND│ │AND│ │AND│
│ └───┘ └───┘ └───┘ └───┘
│ ┌────┐ ┌────┐ ┌────┐ ┌────┐
│ │ │ │ │ │ │ │
│ │ HA │ │ FA │ │ FA │ │ HA │
│ │ │ │ │ │ │ │
│ └────┘ └────┘ └────┘ └────┘
─ ─ ─ ─ ─ ─ ─ ─ ─ ┼ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ HORIZONTAL CUT=2
A3B2 A2B2 A1B2 A0B2
┌▼─▼┐ │ ┌───┐ ┌───┐ ┌───┐
│AND│ │AND│ │AND│ │AND│
└┬──┘ │ └───┘ └───┘ └───┘
│
│
│ │ ┌────┐ ┌────┐ ┌────┐
│ │ │ │ │ │ │
│ │ │ FA │ │ FA │ │ HA │
@ -73,13 +73,13 @@ class UnsignedBrokenArrayMultiplier(MultiplierCircuit):
┌▼─▼┐ │ ┌▼─▼┐ │ ┌───┐ ┌───┐
│AND│ │ │AND│ │AND│ │AND│
└┬──┘ │ └┬──┘ │ └───┘ └───┘
│ │ │
│ │ │
┌▼───┐ ┌▼──▼┐ │ ┌────┐ ┌────┐
│ │ │ │ │ │ │ │
┌──────┤ HA │◄────┤ HA │ │ │ FA │ │ HA │
┌──────┤ HA │◄────┤ HA │ │ │ FA │ │ HA │
│ │ │ │ │ │ │ │ │
│ └──┬─┘ └──┬─┘ │ └────┘ └────┘
│ │ │
│ │ │
│ │ │ │
▼ ▼ ▼ ▼ ▼ ▼ ▼ ▼
P7 P6 P5 │ P4=0 P3=0 P2=0 P1=0 P0=0
@ -98,32 +98,32 @@ class UnsignedBrokenArrayMultiplier(MultiplierCircuit):
# NOTE: If horizontal/vertical cut is specified as 0 the final circuit is a simple array multiplier
self.horizontal_cut = horizontal_cut
self.vertical_cut = vertical_cut
self.N = max(a.N, b.N)
# Horizontal cut level should be: 0 <= horizontal_cut < N
# Vertical cut level should be: horizontal_cut <= vertical_cut < 2*N
assert horizontal_cut < self.N
assert vertical_cut < 2*self.N
# Vertical cut should be greater or equal to horizontal cut
assert vertical_cut >= horizontal_cut
super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, **kwargs)
# Bus sign extension in case buses have different lengths
self.a.bus_extend(N=self.N, prefix=a.prefix)
self.b.bus_extend(N=self.N, prefix=b.prefix)
self.ommited_rows = 0
# Gradual generation of partial products
for b_multiplier_index in range(self.horizontal_cut, self.N):
# Number of elements that should be ommited in the current level based on vertical cut
pp_row_elems_to_skip = self.vertical_cut - b_multiplier_index if self.vertical_cut - b_multiplier_index > 0 else 0
# Number of pp pairs present in the current row
# Number of pp pairs present in the current row
pp_row_elems = self.N-pp_row_elems_to_skip if self.N-pp_row_elems_to_skip > 0 else 0
self.ommited_rows += 1 if pp_row_elems == 0 else 0
for a_multiplicand_index in range((self.N-pp_row_elems), self.N):
for a_multiplicand_index in range((self.N-pp_row_elems), self.N):
# AND gates generation for calculation of partial products
obj_and = AndGate(self.a.get_wire(a_multiplicand_index), self.b.get_wire(b_multiplier_index), prefix=self.prefix+"_and"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_and)
@ -154,7 +154,7 @@ class UnsignedBrokenArrayMultiplier(MultiplierCircuit):
# PRODUCT GENERATION
if (a_multiplicand_index == 0 and b_multiplier_index == self.horizontal_cut) or (self.horizontal_cut + self.ommited_rows == self.N-1):
self.out.connect(a_multiplicand_index + b_multiplier_index, obj_and.out)
# 1 bit multiplier case
if a_multiplicand_index == self.N-1 and b_multiplier_index == self.N-1:
self.out.connect(a_multiplicand_index+b_multiplier_index+1, ConstantWireValue0())
@ -171,150 +171,3 @@ class UnsignedBrokenArrayMultiplier(MultiplierCircuit):
else:
for grounded_out_index in range(0, max(self.horizontal_cut, self.vertical_cut)):
self.out.connect(grounded_out_index, ConstantWireValue0())
class SignedBrokenArrayMultiplier(MultiplierCircuit):
"""Class representing signed broken array multiplier.
It represents an approximative version of signed array multiplier with simpler structure.
It is created by modifying an ordinary N-bit unsigned array multiplier by omitting partial product
stage cells by the specified horizontal and vertical cut levels.
The design promises better area and power parameters in exchange for the loss of computation precision.
The BAM design allows to save more partial product stage adders than truncated multiplier.
TODO
```
A3B0 A2B0 A1B0 A0B0
│ │ │ │ │ │ │ │
┌▼─▼─┐ ┌▼─▼┐ ┌▼─▼┐ ┌▼─▼┐
│NAND│ │AND│ │AND│ │AND│
└┬───┘ └┬──┘ └┬──┘ └─┬─┘
A3B1 │ A2B1 │ A1B1 │ A0B1 │
┌▼─▼─┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │
│NAND│ │ │AND│ │ │AND│ │ │AND│ │
1 └┬───┘ │ └┬──┘ │ └┬──┘ │ └┬──┘ │
│ │ │ │ │ │ │ │ │
┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ │
│ │ │ │ │ │ │ │ │
┌───────┤ FA │◄──┤ FA │◄──┤ FA │◄──┤ HA │ │
│ │ │ │ │ │ │ │ │ │
│ └┬───┘ └┬───┘ └┬───┘ └─┬──┘ │
│ A3B2 │ A2B2 │ A1B2 │ A0B2 │ │
│ ┌▼─▼─┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ │
│ │NAND│ │ │AND│ │ │AND│ │ │AND│ │ │
│ └┬───┘ │ └┬──┘ │ └┬──┘ │ └┬──┘ │ │
│ │ │ │ │ │ │ │ │ │
┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ │ │
│ │ │ │ │ │ │ │ │ │
┌───────┤ FA │◄──┤ FA │◄──┤ FA │◄──┤ HA │ │ │
│ │ │ │ │ │ │ │ │ │ │
│ └┬───┘ └┬───┘ └┬───┘ └─┬──┘ │ │
│ A3B3 │ A2B3 │ A1B3 │ A0B3 │ │ │
│ ┌▼─▼┐ │ ┌▼─▼─┐ │ ┌▼─▼─┐ │ ┌▼─▼─┐ │ │ │
│ │AND│ │ │NAND│ │ │NAND│ │ │NAND│ │ │ │
1 │ └┬──┘ │ └┬───┘ │ └┬───┘ │ └┬───┘ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │
┌─▼──┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │ │
│XOR │◄──┤ FA │◄──┤ FA │◄──┤ FA │◄──┤ HA │ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │ │
└─┬──┘ └─┬──┘ └─┬──┘ └─┬──┘ └─┬──┘ │ │ │
│ │ │ │ │ │ │ │
▼ ▼ ▼ ▼ ▼ ▼ ▼ ▼
P7 P6 P5 P4 P3 P2 P1 P0
```
Description of the __init__ method.
Args:
a (Bus): First input bus.
b (Bus): Second input bus.
horizontal_cut (int, optional): Specifies horizontal cut used in signed broken array multiplier circuit creation. Defaults to 0.
vertical_cut (int, optional): Specifies vertical cut used in signed broken array multiplier circuit creation. Defaults to 0.
prefix (str, optional): Prefix name of signed broken array multiplier. Defaults to "".
name (str, optional): Name of signed broken array multiplier. Defaults to "s_bam".
"""
def __init__(self, a: Bus, b: Bus, horizontal_cut: int = 0, vertical_cut: int = 0, prefix: str = "", name: str = "s_bam", **kwargs):
# NOTE: If horizontal/vertical cut is specified as 0 the final circuit is a simple array multiplier
self.horizontal_cut = horizontal_cut
self.vertical_cut = vertical_cut
self.N = max(a.N, b.N)
# Horizontal cut level should be: 0 <= horizontal_cut < N
# Vertical cut level should be: horizontal_cut <= vertical_cut < 2*N
assert horizontal_cut < self.N
assert vertical_cut < 2*self.N
# Vertical cut should be greater or equal to horizontal cut
assert vertical_cut >= horizontal_cut
super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, signed=True, **kwargs)
# Bus sign extension in case buses have different lengths
self.a.bus_extend(N=self.N, prefix=a.prefix)
self.b.bus_extend(N=self.N, prefix=b.prefix)
self.ommited_rows = 0
# Gradual generation of partial products
for b_multiplier_index in range(self.horizontal_cut, self.N):
# Number of elements that should be ommited in the current level based on vertical cut
pp_row_elems_to_skip = self.vertical_cut - b_multiplier_index if self.vertical_cut - b_multiplier_index > 0 else 0
# Number of pp pairs present in the current row
pp_row_elems = self.N-pp_row_elems_to_skip if self.N-pp_row_elems_to_skip > 0 else 0
self.ommited_rows += 1 if pp_row_elems == 0 else 0
for a_multiplicand_index in range(self.N-pp_row_elems, self.N):
# AND and NAND gates generation for calculation of partial products and sign extension
if (b_multiplier_index == self.N-1 and a_multiplicand_index != self.N-1) or (b_multiplier_index != self.N-1 and a_multiplicand_index == self.N-1):
obj_nand = NandGate(self.a.get_wire(a_multiplicand_index), self.b.get_wire(b_multiplier_index), prefix=self.prefix+"_nand"+str(a_multiplicand_index)+"_"+str(b_multiplier_index), parent_component=self)
self.add_component(obj_nand)
else:
obj_and = AndGate(self.a.get_wire(a_multiplicand_index), self.b.get_wire(b_multiplier_index), prefix=self.prefix+"_and"+str(a_multiplicand_index)+"_"+str(b_multiplier_index), parent_component=self)
self.add_component(obj_and)
if b_multiplier_index != self.horizontal_cut + self.ommited_rows:
if b_multiplier_index == self.horizontal_cut + self.ommited_rows + 1:
previous_product = self.components[a_multiplicand_index + b_multiplier_index - self.vertical_cut].out
else:
previous_product = self.get_previous_partial_product(a_index=a_multiplicand_index, b_index=b_multiplier_index, mult_type="bam")
# HA generation for first 1-bit adder in each row starting from the second one
if a_multiplicand_index == 0 or self.vertical_cut-b_multiplier_index == a_multiplicand_index:
obj_adder = HalfAdder(self.get_previous_component().out, previous_product, prefix=self.prefix+"_ha"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_adder)
# Product generation
self.out.connect(b_multiplier_index, obj_adder.get_sum_wire())
# FA generation
else:
# Constant wire with value 1 used at the last FA in second row (as one of its inputs) for signed multiplication (based on Baugh Wooley algorithm)
if a_multiplicand_index == self.N-1 and b_multiplier_index == self.horizontal_cut+self.ommited_rows+1:
previous_product = ConstantWireValue1()
obj_adder = FullAdder(self.get_previous_component().out, previous_product, self.get_previous_component(number=2).get_carry_wire(), prefix=self.prefix+"_fa"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_adder)
# PRODUCT GENERATION
if (a_multiplicand_index == 0 and b_multiplier_index == self.horizontal_cut) or (self.horizontal_cut + self.ommited_rows == self.N-1):
self.out.connect(a_multiplicand_index + b_multiplier_index, obj_and.out)
# 1 bit multiplier case
if a_multiplicand_index == self.N-1 and b_multiplier_index == self.N-1:
obj_nor = NorGate(ConstantWireValue1(), self.get_previous_component().out, prefix=self.prefix+"_nor_zero_extend", parent_component=self)
self.add_component(obj_nor)
self.out.connect(a_multiplicand_index+1, obj_nor.out)
elif b_multiplier_index == self.N-1 and self.horizontal_cut != self.N-1:
self.out.connect(b_multiplier_index + a_multiplicand_index, obj_adder.get_sum_wire())
if a_multiplicand_index == self.N-1:
obj_xor = XorGate(self.get_previous_component().get_carry_wire(), ConstantWireValue1(), prefix=self.prefix+"_xor"+str(a_multiplicand_index+1)+"_"+str(b_multiplier_index), parent_component=self)
self.add_component(obj_xor)
self.out.connect(self.out.N-1, obj_xor.out)
# Connecting the output bits generated from ommited cells to ground
if self.vertical_cut == 2*self.N-1:
[self.out.connect(out_id, ConstantWireValue0()) for out_id in range(self.out.N)]
else:
for grounded_out_index in range(0, max(self.horizontal_cut, self.vertical_cut)):
self.out.connect(grounded_out_index, ConstantWireValue0())

220
ariths_gen/multi_bit_circuits/approximate_multipliers/broken_carry_save_multiplier.py Normal file
View File

@ -0,0 +1,220 @@
from ariths_gen.wire_components import (
Wire,
ConstantWireValue0,
ConstantWireValue1,
Bus
)
from ariths_gen.core.arithmetic_circuits import (
ArithmeticCircuit,
MultiplierCircuit,
)
from ariths_gen.core.logic_gate_circuits import (
TwoInputLogicGate
)
from ariths_gen.one_bit_circuits.one_bit_components import (
HalfAdder,
FullAdder,
FullAdderPG
)
from ariths_gen.one_bit_circuits.logic_gates import (
AndGate,
NandGate,
OrGate,
NorGate,
XorGate,
XnorGate,
NotGate
)
from ariths_gen.multi_bit_circuits.adders import (
UnsignedCarryLookaheadAdder
)
class UnsignedBrokenCarrySaveMultiplier(MultiplierCircuit):
"""Class representing unsigned broken carry save (Braun) multiplier.
It represents an approximative version of unsigned carry save multiplier with simpler structure.
It is created by modifying an ordinary N-bit unsigned carry save multiplier by omitting partial product
stage cells by the specified horizontal and vertical cut levels.
The design promises better area and power parameters in exchange for the loss of computation precision.
The BCSM design allows to save more partial product stage adders than truncated multiplier architectures.
```
VERTICAL CUT=3
│
A3B0 A2B0 A1B0 A0B0
┌───┐ │┌───┐ ┌───┐ ┌───┐
│AND│ │AND│ │AND│ │AND│
└───┘ │└───┘ └───┘ └───┘
│
A3B1 A2B1 A1B1 A0B1
┌───┐ ┌───┐│ ┌───┐ ┌───┐
│AND│ │AND│ │AND│ │AND│
└───┘ └───┘│ └───┘ └───┘
┌────┐ │ ┌────┐ ┌────┐
│ │ │ │ │ │
│ HA │ │ │ HA │ │ HA │
│ │ │ │ │ │
└────┘ │ └────┘ └────┘
─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─┼─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ HORIZONTAL CUT=2
A3B2 A2B2 A1B2 A0B2
┌▼─▼┐ ┌▼─▼┐ ┌▼─▼┐ │ ┌───┐
│AND│ │AND│ │AND│ │AND│
└┬──┘ └┬──┘ └┬──┘ │ └───┘
│ │ │
A3B3 │ A2B3 │ A1B3 │ A0B3 │ ┌────┐
┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ │
│AND│ │ │AND│ │ │AND│ │ │AND│ │ │ HA │
└┬──┘ │ └┬──┘ │ └┬──┘ │ └┬──┘ │ │
│ │ │ │ │ │ │ │ └────┘
│ │ │ │ │ │ │
│ │ │ │ │ │ │ │
│ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐
│ │ │ │ │ │ │ │
│ ┌─┤ HA │ ┌─┤ HA │ ┌─┤ HA │
│ │ │ │ │ │ │ │ │ │ │
0 0 │ │ └─┬──┘ │ └─┬──┘ │ └──┬─┘
│ │ │S2 │C2 │S1 │C1 │S0 │C0 │ │
┌──▼──▼───▼────▼───▼──────▼───▼──────▼──┐ │
│ Carry-propagate │ │ │
│ adder │ │
└─┬───────┬──────────┬──────────┬───────┘ │ │
│ │ │ │ │
│ │ │ │ │ │
│ │ │ │ │
│ │ │ │ │ │
▼ ▼ ▼ ▼ ▼ ▼ ▼ ▼
P7 P6 P5 P4 P3 │ P2=0 P1=0 P0=0
```
Description of the __init__ method.
Args:
a (Bus): First input bus.
b (Bus): Second input bus.
horizontal_cut (int, optional): Specifies horizontal cut used in broken carry save multiplier circuit creation. Defaults to 0.
vertical_cut (int, optional): Specifies vertical cut used in broken carry save multiplier circuit creation. Defaults to 0.
prefix (str, optional): Prefix name of unsigned broken carry save multiplier. Defaults to "".
name (str, optional): Name of unsigned broken carry save multiplier. Defaults to "u_bamcsa".
unsigned_adder_class_name (str, optional): Unsigned multi bit adder used for final vector merging of sums and carries. Defaults to UnsignedCarryLookaheadAdder.
"""
def __init__(self, a: Bus, b: Bus, horizontal_cut: int = 0, vertical_cut: int = 0, prefix: str = "", name: str = "u_bamcsa", unsigned_adder_class_name: str = UnsignedCarryLookaheadAdder, **kwargs):
# NOTE: If horizontal/vertical cut is specified as 0 the final circuit is a simple carry save multiplier
self.horizontal_cut = horizontal_cut
self.vertical_cut = vertical_cut
self.N = max(a.N, b.N)
# Horizontal cut level should be: 0 <= horizontal_cut < N
# Vertical cut level should be: horizontal_cut <= vertical_cut < 2*N
assert horizontal_cut < self.N
assert vertical_cut < 2*self.N
# Vertical cut should be greater or equal to horizontal cut
assert vertical_cut >= horizontal_cut
super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, **kwargs)
# Bus sign extension in case buses have different lengths
self.a.bus_extend(N=self.N, prefix=a.prefix)
self.b.bus_extend(N=self.N, prefix=b.prefix)
self.ommited_rows = self.horizontal_cut
# Gradual generation of partial products
for b_multiplier_index in range(self.horizontal_cut, self.N):
# Number of elements that should be ommited in the current level based on vertical cut
pp_row_elems_to_skip = self.vertical_cut - b_multiplier_index if self.vertical_cut - b_multiplier_index > 0 else 0
# Number of pp pairs present in the current row
pp_row_elems = self.N-pp_row_elems_to_skip if self.N-pp_row_elems_to_skip > 0 else 0
self.ommited_rows += 1 if pp_row_elems == 0 else 0
row_pp_ord = 0
for a_multiplicand_index in range((self.N-pp_row_elems), self.N):
row_pp_ord += 1
# AND gates generation for calculation of partial products
obj_and = AndGate(self.a.get_wire(a_multiplicand_index), self.b.get_wire(b_multiplier_index), prefix=self.prefix+"_and"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_and)
if a_multiplicand_index == 0:
self.out.connect(a_multiplicand_index + b_multiplier_index, obj_and.out)
# HAs generation for first row of adders (the second row in total, first contains just pp generation)
if b_multiplier_index == self.horizontal_cut+1 and a_multiplicand_index != self.N-1:
previous_product = self.get_previous_component(self.N-(pp_row_elems_to_skip+1)+row_pp_ord).out
obj_adder = HalfAdder(a=obj_and.out, b=previous_product, prefix=self.prefix+"_ha"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_adder)
if (a_multiplicand_index == 0):
self.out.connect(b_multiplier_index, obj_adder.get_sum_wire())
# FAs generation for the remaining rows
elif b_multiplier_index > self.horizontal_cut+1 and a_multiplicand_index != self.N-1:
previous_sum = self.get_previous_component((self.N-(pp_row_elems_to_skip+1))*2-1).get_sum_wire() if a_multiplicand_index != self.N-2 else self.get_previous_component((self.N-(pp_row_elems_to_skip+1))*2).out
if a_multiplicand_index == self.N-pp_row_elems and b_multiplier_index <= vertical_cut:
obj_adder = HalfAdder(a=obj_and.out, b=previous_sum, prefix=self.prefix+"_ha"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.out.connect(b_multiplier_index, obj_adder.get_sum_wire())
else:
previous_carry = self.get_previous_component((row_pp_ord*2-1)+((self.N-(a_multiplicand_index+1))*2)).get_carry_wire()
obj_adder = FullAdder(a=obj_and.out, b=previous_sum, c=previous_carry, prefix=self.prefix+"_fa"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_adder)
if (a_multiplicand_index == 0):
self.out.connect(b_multiplier_index, obj_adder.get_sum_wire())
# PRODUCT GENERATION
# 1 bit multiplier case
if (a_multiplicand_index == 0 and b_multiplier_index == self.horizontal_cut) and (self.horizontal_cut + self.ommited_rows == self.N-1):
self.out.connect(a_multiplicand_index + b_multiplier_index, obj_and.out)
if a_multiplicand_index == self.N-1 and b_multiplier_index == self.N-1:
self.out.connect(a_multiplicand_index+b_multiplier_index+1, ConstantWireValue0())
# If architecture is cut to just a row of AND gates
elif self.ommited_rows == self.N-1:
self.out.connect(b_multiplier_index + a_multiplicand_index, obj_and.out)
if a_multiplicand_index == self.N-1:
self.out.connect(self.out.N-1, ConstantWireValue0())
# Connecting the output bits generated from ommited cells to ground
if self.vertical_cut == 2*self.N-1:
[self.out.connect(out_id, ConstantWireValue0()) for out_id in range(self.out.N)]
else:
for grounded_out_index in range(0, max(self.horizontal_cut, self.vertical_cut)):
self.out.connect(grounded_out_index, ConstantWireValue0())
# Final addition of remaining bits using chosen unsigned multi bit adder
final_cpa_N = self.out.N - max(self.N, self.vertical_cut+1)
if self.ommited_rows != self.N-1:
previous_sums = []
previous_carries = []
for wire_id in range(final_cpa_N):
if (wire_id == final_cpa_N-1):
previous_sums.append(ConstantWireValue0())
else:
prev_sum_obj = self.get_previous_component((final_cpa_N-2-wire_id)*2) if wire_id < final_cpa_N-2 else self.get_previous_component()
if isinstance(prev_sum_obj, TwoInputLogicGate):
previous_sums.append(prev_sum_obj.out)
else:
previous_sums.append(prev_sum_obj.get_sum_wire())
if (wire_id == final_cpa_N-1 or (self.vertical_cut+1 == self.out.N-final_cpa_N and wire_id == 0)):
previous_carries.append(ConstantWireValue0())
else:
prev_carry_obj = self.get_previous_component((final_cpa_N-2-wire_id)*2+2)
if isinstance(prev_carry_obj, TwoInputLogicGate):
previous_carries.append(prev_carry_obj.out)
else:
previous_carries.append(prev_carry_obj.get_carry_wire())
# Obtain proper adder name with its bit width (columns bit pairs minus the first alone bit)
adder_name = unsigned_adder_class_name(a=a, b=b).prefix + str(final_cpa_N)
adder_a = Bus(prefix=f"a", wires_list=previous_sums)
adder_b = Bus(prefix=f"b", wires_list=previous_carries)
final_adder = unsigned_adder_class_name(a=adder_a, b=adder_b, prefix=self.prefix, name=adder_name, inner_component=True)
self.add_component(final_adder)
[self.out.connect(o, final_adder.out.get_wire(o-max(self.N, self.vertical_cut)), inserted_wire_desired_index=o-max(self.N, self.vertical_cut)) for o in range(max(self.N, self.vertical_cut), self.out.N)]

140
ariths_gen/multi_bit_circuits/approximate_multipliers/truncated_array_multiplier.py Normal file
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from ariths_gen.wire_components import (
Wire,
ConstantWireValue0,
ConstantWireValue1,
Bus
)
from ariths_gen.core.arithmetic_circuits import (
ArithmeticCircuit,
MultiplierCircuit
)
from ariths_gen.one_bit_circuits.one_bit_components import (
HalfAdder,
FullAdder,
FullAdderPG
)
from ariths_gen.one_bit_circuits.logic_gates import (
AndGate,
NandGate,
OrGate,
NorGate,
XorGate,
XnorGate,
NotGate
)
class UnsignedTruncatedArrayMultiplier(MultiplierCircuit):
"""Class representing unsigned truncated array multiplier.
It represents an approximative version of unsigned array multiplier with simpler structure.
It is created by modifying an ordinary N-bit unsigned array multiplier by ignoring
(truncating) some of the partial products.
The design promises better area and power parameters in exchange for the loss of computation precision.
```
CUT=2
A3B0 A2B0 │ A1B0 A0B0
┌───┐ ┌───┐ ┌───┐ ┌───┐
│AND│ │AND│ │ │AND│ │AND│
└───┘ └───┘ └───┘ └───┘
┌ ─ ─ ─ ┘
A3B1 A2B1 A1B1 A0B1
┌───┐ ┌───┐ │ ┌───┐ ┌───┐
│AND│ │AND│ │AND│ │AND│
└───┘ └───┘ │ └───┘ └───┘
┌────┐ ┌────┐ ┌────┐ ┌────┐
│ │ │ │ │ │ │ │ │
│ HA │ │ FA │ │ FA │ │ HA │
│ │ │ │ │ │ │ │ │
└────┘ └────┘ └────┘ └────┘
─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─┬ ─ ─ ─ ─ ┴─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ CUT=2
A3B2 A2B2 A1B2 A0B2
┌▼─▼┐ ┌▼─▼┐ │ ┌───┐ ┌───┐
│AND│ │AND│ │AND│ │AND│
└┬──┘ └┬──┘ │ └───┘ └───┘
│ │ ┌────┐ ┌────┐
│ │ │ │ │ │ │
│ ┌ ─ ┼─ ─ ─ ┘ │ FA │ │ HA │
│ │ │ │ │ │
│ │ │ └────┘ └────┘
A3B3 │ A2B3 │ A1B3 A0B3
┌▼─▼┐ │ ┌▼─▼┐ │ │ ┌───┐ ┌───┐
│AND│ │ │AND│ │ │AND│ │AND│
└┬──┘ │ └┬──┘ │ │ └───┘ └───┘
┌───▼┐ ┌▼──▼┐ ┌┼───┐ ┌────┐
│ │ │ │ │ ││ │ │ │
┌──────┤ HA │◄────┤ HA │ ││FA │ │ HA │
│ │ │ │ │ │ ││ │ │ │
│ └──┬─┘ └──┬─┘ └┼───┘ └────┘
│ │ │ │ │
▼ ▼ ▼ ▼ ▼ ▼ ▼ ▼
P7 P6 P5 │ P4 P3=0 P2=0 P1=0 P0=0
```
Description of the __init__ method.
Args:
a (Bus): First input bus.
b (Bus): Second input bus.
truncation_cut (int, optional): Specifies truncation cut level used in the truncated array multiplier circuit creation. Note: If equal to 0, the final circuit behaves as an ordinary array multiplier. Defaults to 0.
prefix (str, optional): Prefix name of unsigned truncated array multiplier. Defaults to "".
name (str, optional): Name of unsigned truncated array multiplier. Defaults to "u_tm".
"""
def __init__(self, a: Bus, b: Bus, truncation_cut: int = 0, prefix: str = "", name: str = "u_tm", **kwargs):
# NOTE: If truncation_cut is specified as 0 the final circuit is a simple array multiplier
self.truncation_cut = truncation_cut
self.N = max(a.N, b.N)
# Cut level should be: 0 <= truncation_cut < N
assert truncation_cut < self.N
super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, **kwargs)
# Bus sign extension in case buses have different lengths
self.a.bus_extend(N=self.N, prefix=a.prefix)
self.b.bus_extend(N=self.N, prefix=b.prefix)
# Gradual generation of partial products
for b_multiplier_index in range(self.truncation_cut, self.N):
for a_multiplicand_index in range(self.truncation_cut, self.N):
# AND gates generation for calculation of partial products
obj_and = AndGate(self.a.get_wire(a_multiplicand_index), self.b.get_wire(b_multiplier_index), prefix=self.prefix+"_and"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_and)
if b_multiplier_index != self.truncation_cut:
previous_product = self.components[a_multiplicand_index + b_multiplier_index - 2*self.truncation_cut].out if b_multiplier_index == self.truncation_cut + 1 else self.get_previous_partial_product(a_index=a_multiplicand_index, b_index=b_multiplier_index, mult_type="tm")
# HA generation for first 1-bit adder in each row starting from the second one
if a_multiplicand_index == self.truncation_cut:
obj_adder = HalfAdder(self.get_previous_component().out, previous_product, prefix=self.prefix+"_ha"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_adder)
# Product generation
self.out.connect(b_multiplier_index + self.truncation_cut, obj_adder.get_sum_wire())
# HA generation, last 1-bit adder in second row
elif a_multiplicand_index == self.N-1 and b_multiplier_index == self.truncation_cut+1:
obj_adder = HalfAdder(self.get_previous_component().out, self.get_previous_component(number=2).get_carry_wire(), prefix=self.prefix+"_ha"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_adder)
# FA generation
else:
obj_adder = FullAdder(self.get_previous_component().out, previous_product, self.get_previous_component(number=2).get_carry_wire(), prefix=self.prefix+"_fa"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_adder)
# PRODUCT GENERATION
if (a_multiplicand_index == self.truncation_cut and b_multiplier_index == self.truncation_cut) or (self.truncation_cut == self.N-1):
self.out.connect(a_multiplicand_index + b_multiplier_index, obj_and.out)
# 1 bit multiplier case
if a_multiplicand_index == self.N-1 and b_multiplier_index == self.N-1:
self.out.connect(a_multiplicand_index+b_multiplier_index+1, ConstantWireValue0())
elif b_multiplier_index == self.N-1 and self.truncation_cut != self.N-1:
self.out.connect(b_multiplier_index + a_multiplicand_index, obj_adder.get_sum_wire())
if a_multiplicand_index == self.N-1:
self.out.connect(self.out.N-1, obj_adder.get_carry_wire())
# Connecting the output bits generated from ommited cells to ground
for grounded_out_index in range(0, self.truncation_cut*2):
self.out.connect(grounded_out_index, ConstantWireValue0())

171
ariths_gen/multi_bit_circuits/approximate_multipliers/truncated_carry_save_multiplier.py Normal file
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from ariths_gen.wire_components import (
Wire,
ConstantWireValue0,
ConstantWireValue1,
Bus
)
from ariths_gen.core.arithmetic_circuits import (
ArithmeticCircuit,
MultiplierCircuit
)
from ariths_gen.one_bit_circuits.one_bit_components import (
HalfAdder,
FullAdder,
FullAdderPG
)
from ariths_gen.one_bit_circuits.logic_gates import (
AndGate,
NandGate,
OrGate,
NorGate,
XorGate,
XnorGate,
NotGate
)
from ariths_gen.multi_bit_circuits.adders import (
UnsignedCarryLookaheadAdder
)
class UnsignedTruncatedCarrySaveMultiplier(MultiplierCircuit):
"""Class representing unsigned truncated carry save (Braun) multiplier.
It represents an approximative version of unsigned carry save multiplier with simpler structure.
It is created by modifying an ordinary N-bit unsigned carry save multiplier by ignoring
(truncating) some of the partial products.
The design promises better area and power parameters in exchange for the loss of computation precision.
```
CUT=1
A3B0 A2B0 A1B0 │ A0B0
┌───┐ ┌───┐ ┌───┐ ┌───┐
│AND│ │AND│ │AND│ │ │AND│
└───┘ └───┘ └───┘ └───┘
─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─┬─ ─ ┴ ─ ─ ─ ─ ─ ─ CUT=1
A3B1 A2B1 A1B1 A0B1
┌▼─▼┐ ┌▼─▼┐ ┌▼─▼┐ │ ┌───┐
│AND│ │AND│ │AND│ │AND│
└┬──┘ └┬──┘ └┬──┘ │ └───┘
│ │ │ ┌────┐
┌───┘ │ │ │ │ │
│ ┌─┘ │ │ HA │
│ │ │ │ │ │
│ │ │ └────┘
│ │ ┌ ─ ─│─ ─ ┘
A3B2 │ A2B2 │ A1B2 │ A0B2
┌▼─▼┐ │ ┌▼─▼┐ │ ┌───┐ │ │┌───┐
│AND│ │ │AND│ │ │AND│ ││AND│
└┬──┘ │ └┬──┘ │ └┬──┘ │ │└───┘
│ ┌▼──▼┐ ┌▼──▼┐ ┌──┼─┐
│ │ │ │ │ │ │ │ │
│ ┌─┤ HA │ ┌─┤ HA │ │FA│ │
│ │ │ │ │ │ │ │ │ │ │
│ │ └───┬┘ │ └───┬┘ └──┼─┘
│ │ │ │ │ │ │
│ │ │ │ ┌│─ ─ ┘ │
A3B3 │ A2B3│ │ A1B3│ │ A0B3 │
┌▼─▼┐ │ ┌▼─▼┐│ │ ┌▼─▼┐│ ││┌───┐ │
│AND│ │ │AND││ │ │AND││ ││AND│ │
└┬──┘ │ └┬──┘│ │ └┬──┘│ ┌─ ┘│└───┘ │
│ ┌▼──▼┐ │ ┌▼──▼┐ │ │ ┌─┼──┐ │
│ │ │ │ │ │ │ │ │ │ │
│ ┌──┤ FA │◄─┘ ┌─┤ FA │◄─┘ │ │ │FA│ │
│ │ │ │ │ │ │ │ │ │ │
│ │ └──┬─┘ │ └──┬─┘ │ └─┼──┘ │
│ │ │ │ │ │ │ │
│ │ │ │ │ │ │
│ │ │ │ │ │ │
0 0 │ │ │ │ │ │ │ │
│ │ │S1 │C1 │S0 │C0 │ │ │
┌─▼───▼───▼────▼─────▼───────▼─┐ │ │ │ │
│ Carry-propagate │ │ │ │
│ adder │ │ │ │ │
└─────┬────────┬─────────┬─────┘ │ │ │
▼ ▼ ▼ ▼ │ ▼ ▼ ▼ ▼
P7 P6 P5 P4 P3 P2 P1=0 P0=0
```
Description of the __init__ method.
Args:
a (Bus): First input bus.
b (Bus): Second input bus.
truncation_cut (int, optional): Specifies truncation cut level used in the truncated carry save multiplier circuit creation. Note: If equal to 0, the final circuit behaves as an ordinary carry save multiplier. Defaults to 0.
prefix (str, optional): Prefix name of unsigned truncated carry save multiplier. Defaults to "".
name (str, optional): Name of unsigned truncated carry save multiplier. Defaults to "u_tm".
unsigned_adder_class_name (str, optional): Unsigned multi bit adder used for final vector merging of sums and carries. Defaults to UnsignedCarryLookaheadAdder.
"""
def __init__(self, a: Bus, b: Bus, truncation_cut: int = 0, prefix: str = "", name: str = "u_tmcsa", unsigned_adder_class_name: str = UnsignedCarryLookaheadAdder, **kwargs):
# NOTE: If truncation_cut is specified as 0 the final circuit is a simple carry save multiplier
self.truncation_cut = truncation_cut
self.N = max(a.N, b.N)
# Cut level should be: 0 <= truncation_cut < N
assert truncation_cut < self.N
super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, **kwargs)
# Bus sign extension in case buses have different lengths
self.a.bus_extend(N=self.N, prefix=a.prefix)
self.b.bus_extend(N=self.N, prefix=b.prefix)
# Gradual generation of partial products
for b_multiplier_index in range(self.truncation_cut, self.N):
row_pp_ord = 0
for a_multiplicand_index in range(self.truncation_cut, self.N):
row_pp_ord += 1
# AND gates generation for calculation of partial products
obj_and = AndGate(self.a.get_wire(a_multiplicand_index), self.b.get_wire(b_multiplier_index), prefix=self.prefix+"_and"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_and)
if a_multiplicand_index == self.truncation_cut:
self.out.connect(b_multiplier_index+self.truncation_cut, obj_and.out)
# HAs generation for first row of adders (the second row in total, first contains just pp generation)
if b_multiplier_index == self.truncation_cut+1 and a_multiplicand_index != self.N-1:
previous_product = self.get_previous_component((self.N-a_multiplicand_index-1)+(row_pp_ord*2-1)).out
obj_adder = HalfAdder(a=obj_and.out, b=previous_product, prefix=self.prefix+"_ha"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_adder)
if (a_multiplicand_index == self.truncation_cut):
self.out.connect(b_multiplier_index+self.truncation_cut, obj_adder.get_sum_wire())
# FAs generation for the remaining rows
elif b_multiplier_index > self.truncation_cut+1 and a_multiplicand_index != self.N-1:
previous_sum = self.get_previous_component((self.N-(truncation_cut+1))*2-1).get_sum_wire() if a_multiplicand_index != self.N-2 else self.get_previous_component((self.N-(truncation_cut+1))*2).out
previous_carry = self.get_previous_component((self.N-truncation_cut)*2-1).get_carry_wire()
obj_adder = FullAdder(a=obj_and.out, b=previous_sum, c=previous_carry, prefix=self.prefix+"_fa"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_adder)
if (a_multiplicand_index == self.truncation_cut):
self.out.connect(b_multiplier_index+self.truncation_cut, obj_adder.get_sum_wire())
# PRODUCT GENERATION
# 1 bit multiplier case
if (a_multiplicand_index == self.truncation_cut and b_multiplier_index == self.truncation_cut) or (self.truncation_cut == self.N-1):
self.out.connect(a_multiplicand_index + b_multiplier_index, obj_and.out)
# 1 bit multiplier case
if a_multiplicand_index == self.N-1 and b_multiplier_index == self.N-1:
self.out.connect(a_multiplicand_index+b_multiplier_index+1, ConstantWireValue0())
# Connecting the output bits generated from ommited cells to ground
for grounded_out_index in range(0, self.truncation_cut*2):
self.out.connect(grounded_out_index, ConstantWireValue0())
# Final addition of remaining bits using chosen unsigned multi bit adder
if self.truncation_cut != self.N-1:
final_cpa_N = self.N - self.truncation_cut
previous_sums = [self.get_previous_component((final_cpa_N-2-wire_id)*2).get_sum_wire() if wire_id < final_cpa_N-2 else self.get_previous_component().out if wire_id == final_cpa_N-2 else ConstantWireValue0() for wire_id in range(final_cpa_N)]
previous_carries = [self.get_previous_component((final_cpa_N-2-wire_id)*2+2).get_carry_wire() if wire_id != final_cpa_N-1 else ConstantWireValue0() for wire_id in range(final_cpa_N)]
# Obtain proper adder name with its bit width (columns bit pairs minus the first alone bit)
adder_name = unsigned_adder_class_name(a=a, b=b).prefix + str(final_cpa_N)
adder_a = Bus(prefix=f"a", wires_list=previous_sums)
adder_b = Bus(prefix=f"b", wires_list=previous_carries)
final_adder = unsigned_adder_class_name(a=adder_a, b=adder_b, prefix=self.prefix, name=adder_name, inner_component=True)
self.add_component(final_adder)
[self.out.connect(o, final_adder.out.get_wire(o-(self.N+self.truncation_cut)), inserted_wire_desired_index=o-(self.N+self.truncation_cut)) for o in range(self.N+self.truncation_cut, self.out.N)]

269
ariths_gen/multi_bit_circuits/approximate_multipliers/truncated_multiplier.py
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@ -1,269 +0,0 @@
from ariths_gen.wire_components import (
Wire,
ConstantWireValue0,
ConstantWireValue1,
Bus
)
from ariths_gen.core.arithmetic_circuits import (
ArithmeticCircuit,
MultiplierCircuit
)
from ariths_gen.one_bit_circuits.one_bit_components import (
HalfAdder,
FullAdder,
FullAdderPG
)
from ariths_gen.one_bit_circuits.logic_gates import (
AndGate,
NandGate,
OrGate,
NorGate,
XorGate,
XnorGate,
NotGate
)
from ariths_gen.multi_bit_circuits.multipliers import(
UnsignedArrayMultiplier,
SignedArrayMultiplier
)
class UnsignedTruncatedMultiplier(MultiplierCircuit):
"""Class representing unsigned truncated multiplier.
It represents an approximative version of unsigned array multiplier with simpler structure.
It is created by modifying an ordinary N-bit unsigned array multiplier by ignoring
(truncating) some of the partial products.
The design promises better area and power parameters in exchange for the loss of computation precision.
```
CUT=2
A3B0 A2B0 │ A1B0 A0B0
┌───┐ ┌───┐ ┌───┐ ┌───┐
│AND│ │AND│ │ │AND│ │AND│
└───┘ └───┘ └───┘ └───┘
┌ ─ ─ ─ ┘
A3B1 A2B1 A1B1 A0B1
┌───┐ ┌───┐ │ ┌───┐ ┌───┐
│AND│ │AND│ │AND│ │AND│
└───┘ └───┘ │ └───┘ └───┘
┌────┐ ┌────┐ ┌────┐ ┌────┐
│ │ │ │ │ │ │ │ │
│ HA │ │ FA │ │ FA │ │ HA │
│ │ │ │ │ │ │ │ │
└────┘ └────┘ └────┘ └────┘
─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─┬ ─ ─ ─ ─ ┴─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ CUT=2
A3B2 A2B2 A1B2 A0B2
┌▼─▼┐ ┌▼─▼┐ │ ┌───┐ ┌───┐
│AND│ │AND│ │AND│ │AND│
└┬──┘ └┬──┘ │ └───┘ └───┘
│ │ ┌────┐ ┌────┐
│ │ │ │ │ │ │
│ ┌ ─ ┼─ ─ ─ ┘ │ FA │ │ HA │
│ │ │ │ │ │
│ │ │ └────┘ └────┘
A3B3 │ A2B3 │ A1B3 A0B3
┌◄─►┐ │ ┌◄─►┐ │ │ ┌───┐ ┌───┐
│AND│ │ │AND│ │ │AND│ │AND│
└┬──┘ │ └┬──┘ │ │ └───┘ └───┘
┌───▼┐ ┌▼──▼┐ ┌┼───┐ ┌────┐
│ │ │ │ │ ││ │ │ │
┌──────┤ HA │◄────┤ HA │ ││FA │ │ HA │
│ │ │ │ │ │ ││ │ │ │
│ └──┬─┘ └──┬─┘ └┼───┘ └────┘
│ │ │ │ │
▼ ▼ ▼ ▼ ▼ ▼ ▼ ▼
P7 P6 P5 │ P4 P3=0 P2=0 P1=0 P0=0
```
Description of the __init__ method.
Args:
a (Bus): First input bus.
b (Bus): Second input bus.
truncation_cut (int, optional): Specifies truncation cut level used in the truncated multiplier circuit creation. Note: If equal to 0, the final circuit behaves as an ordinary array multiplier. Defaults to 0.
prefix (str, optional): Prefix name of unsigned truncated multiplier. Defaults to "".
name (str, optional): Name of unsigned truncated multiplier. Defaults to "u_tm".
"""
def __init__(self, a: Bus, b: Bus, truncation_cut: int = 0, prefix: str = "", name: str = "u_tm", **kwargs):
# NOTE: If truncation_cut is specified as 0 the final circuit is a simple array multiplier
self.truncation_cut = truncation_cut
self.N = max(a.N, b.N)
# Cut level should be: 0 <= truncation_cut < N
assert truncation_cut < self.N
super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, **kwargs)
# Bus sign extension in case buses have different lengths
self.a.bus_extend(N=self.N, prefix=a.prefix)
self.b.bus_extend(N=self.N, prefix=b.prefix)
# Gradual generation of partial products
for b_multiplier_index in range(self.truncation_cut, self.N):
for a_multiplicand_index in range(self.truncation_cut, self.N):
# AND gates generation for calculation of partial products
obj_and = AndGate(self.a.get_wire(a_multiplicand_index), self.b.get_wire(b_multiplier_index), prefix=self.prefix+"_and"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_and)
if b_multiplier_index != self.truncation_cut:
previous_product = self.components[a_multiplicand_index + b_multiplier_index - 2*self.truncation_cut].out if b_multiplier_index == self.truncation_cut + 1 else self.get_previous_partial_product(a_index=a_multiplicand_index, b_index=b_multiplier_index, mult_type="tm")
# HA generation for first 1-bit adder in each row starting from the second one
if a_multiplicand_index == self.truncation_cut:
obj_adder = HalfAdder(self.get_previous_component().out, previous_product, prefix=self.prefix+"_ha"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_adder)
# Product generation
self.out.connect(b_multiplier_index + self.truncation_cut, obj_adder.get_sum_wire())
# HA generation, last 1-bit adder in second row
elif a_multiplicand_index == self.N-1 and b_multiplier_index == self.truncation_cut+1:
obj_adder = HalfAdder(self.get_previous_component().out, self.get_previous_component(number=2).get_carry_wire(), prefix=self.prefix+"_ha"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_adder)
# FA generation
else:
obj_adder = FullAdder(self.get_previous_component().out, previous_product, self.get_previous_component(number=2).get_carry_wire(), prefix=self.prefix+"_fa"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_adder)
# PRODUCT GENERATION
if (a_multiplicand_index == self.truncation_cut and b_multiplier_index == self.truncation_cut) or (self.truncation_cut == self.N-1):
self.out.connect(a_multiplicand_index + b_multiplier_index, obj_and.out)
# 1 bit multiplier case
if a_multiplicand_index == self.N-1 and b_multiplier_index == self.N-1:
self.out.connect(a_multiplicand_index+b_multiplier_index+1, ConstantWireValue0())
elif b_multiplier_index == self.N-1 and self.truncation_cut != self.N-1:
self.out.connect(b_multiplier_index + a_multiplicand_index, obj_adder.get_sum_wire())
if a_multiplicand_index == self.N-1:
self.out.connect(self.out.N-1, obj_adder.get_carry_wire())
# Connecting the output bits generated from ommited cells to ground
for grounded_out_index in range(0, self.truncation_cut*2):
self.out.connect(grounded_out_index, ConstantWireValue0())
class SignedTruncatedMultiplier(MultiplierCircuit):
"""Class representing signed truncated multiplier.
It represents an approximative version of signed array multiplier with simpler structure.
It is created by modifying an ordinary N-bit signed array multiplier by ignoring
(truncating) some of the partial products.
The design promises better area and power parameters in exchange for the loss of computation precision.
```TODO
A3B0 A2B0 A1B0 A0B0
│ │ │ │ │ │ │ │
┌▼─▼─┐ ┌▼─▼┐ ┌▼─▼┐ ┌▼─▼┐
│NAND│ │AND│ │AND│ │AND│
└┬───┘ └┬──┘ └┬──┘ └─┬─┘
A3B1 │ A2B1 │ A1B1 │ A0B1 │
┌▼─▼─┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │
│NAND│ │ │AND│ │ │AND│ │ │AND│ │
1 └┬───┘ │ └┬──┘ │ └┬──┘ │ └┬──┘ │
│ │ │ │ │ │ │ │ │
┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ │
│ │ │ │ │ │ │ │ │
┌───────┤ FA │◄──┤ FA │◄──┤ FA │◄──┤ HA │ │
│ │ │ │ │ │ │ │ │ │
│ └┬───┘ └┬───┘ └┬───┘ └─┬──┘ │
│ A3B2 │ A2B2 │ A1B2 │ A0B2 │ │
│ ┌▼─▼─┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ │
│ │NAND│ │ │AND│ │ │AND│ │ │AND│ │ │
│ └┬───┘ │ └┬──┘ │ └┬──┘ │ └┬──┘ │ │
│ │ │ │ │ │ │ │ │ │
┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ │ │
│ │ │ │ │ │ │ │ │ │
┌───────┤ FA │◄──┤ FA │◄──┤ FA │◄──┤ HA │ │ │
│ │ │ │ │ │ │ │ │ │ │
│ └┬───┘ └┬───┘ └┬───┘ └─┬──┘ │ │
│ A3B3 │ A2B3 │ A1B3 │ A0B3 │ │ │
│ ┌▼─▼┐ │ ┌▼─▼─┐ │ ┌▼─▼─┐ │ ┌▼─▼─┐ │ │ │
│ │AND│ │ │NAND│ │ │NAND│ │ │NAND│ │ │ │
1 │ └┬──┘ │ └┬───┘ │ └┬───┘ │ └┬───┘ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │
┌─▼──┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │ │
│XOR │◄──┤ FA │◄──┤ FA │◄──┤ FA │◄──┤ HA │ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │ │
└─┬──┘ └─┬──┘ └─┬──┘ └─┬──┘ └─┬──┘ │ │ │
│ │ │ │ │ │ │ │
▼ ▼ ▼ ▼ ▼ ▼ ▼ ▼
P7 P6 P5 P4 P3 P2 P1 P0
```
Description of the __init__ method.
Args:
a (Bus): First input bus.
b (Bus): Second input bus.
truncation_cut (int, optional): Specifies truncation cut level used in the truncated multiplier circuit creation. Note: If equal to 0, the final circuit behaves as an ordinary array multiplier. Defaults to 0.
prefix (str, optional): Prefix name of signed truncated multiplier. Defaults to "".
name (str, optional): Name of signed truncated multiplier. Defaults to "s_tm".
"""
def __init__(self, a: Bus, b: Bus, truncation_cut: int = 0, prefix: str = "", name: str = "s_tm", **kwargs):
# NOTE: If truncation_cut is specified as 0 the final circuit is a simple array multiplier
self.truncation_cut = truncation_cut
self.N = max(a.N, b.N)
# Cut level should be: 0 <= truncation_cut < N
assert truncation_cut < self.N
super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, signed=True, **kwargs)
# Bus sign extension in case buses have different lengths
self.a.bus_extend(N=self.N, prefix=a.prefix)
self.b.bus_extend(N=self.N, prefix=b.prefix)
# Gradual generation of partial products
for b_multiplier_index in range(self.truncation_cut, self.N):
for a_multiplicand_index in range(self.truncation_cut, self.N):
# AND and NAND gates generation for calculation of partial products and sign extension
if (b_multiplier_index == self.N-1 and a_multiplicand_index != self.N-1) or (b_multiplier_index != self.N-1 and a_multiplicand_index == self.N-1):
obj_nand = NandGate(self.a.get_wire(a_multiplicand_index), self.b.get_wire(b_multiplier_index), prefix=self.prefix+"_nand"+str(a_multiplicand_index)+"_"+str(b_multiplier_index), parent_component=self)
self.add_component(obj_nand)
else:
obj_and = AndGate(self.a.get_wire(a_multiplicand_index), self.b.get_wire(b_multiplier_index), prefix=self.prefix+"_and"+str(a_multiplicand_index)+"_"+str(b_multiplier_index), parent_component=self)
self.add_component(obj_and)
if b_multiplier_index != self.truncation_cut:
previous_product = self.components[a_multiplicand_index + b_multiplier_index - 2*self.truncation_cut].out if b_multiplier_index == self.truncation_cut + 1 else self.get_previous_partial_product(a_index=a_multiplicand_index, b_index=b_multiplier_index, mult_type="tm")
# HA generation for first 1-bit adder in each row starting from the second one
if a_multiplicand_index == self.truncation_cut:
obj_adder = HalfAdder(self.get_previous_component().out, previous_product, prefix=self.prefix+"_ha"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_adder)
# Product generation
self.out.connect(b_multiplier_index + self.truncation_cut, obj_adder.get_sum_wire())
# FA generation
else:
# Constant wire with value 1 used at the last FA in second row (as one of its inputs) for signed multiplication (based on Baugh Wooley algorithm)
if a_multiplicand_index == self.N-1 and b_multiplier_index == self.truncation_cut+1:
previous_product = ConstantWireValue1()
obj_adder = FullAdder(self.get_previous_component().out, previous_product, self.get_previous_component(number=2).get_carry_wire(), prefix=self.prefix+"_fa"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_adder)
# PRODUCT GENERATION
if (a_multiplicand_index == self.truncation_cut and b_multiplier_index == self.truncation_cut) or (self.truncation_cut == self.N-1):
self.out.connect(a_multiplicand_index + b_multiplier_index, obj_and.out)
# 1 bit multiplier case
if a_multiplicand_index == self.N-1 and b_multiplier_index == self.N-1:
obj_nor = NorGate(ConstantWireValue1(), self.get_previous_component().out, prefix=self.prefix+"_nor_zero_extend", parent_component=self)
self.add_component(obj_nor)
self.out.connect(a_multiplicand_index+1, obj_nor.out)
elif b_multiplier_index == self.N-1 and self.truncation_cut != self.N-1:
self.out.connect(b_multiplier_index + a_multiplicand_index, obj_adder.get_sum_wire())
if a_multiplicand_index == self.N-1:
obj_xor = XorGate(self.get_previous_component().get_carry_wire(), ConstantWireValue1(), prefix=self.prefix+"_xor"+str(a_multiplicand_index+1)+"_"+str(b_multiplier_index), parent_component=self)
self.add_component(obj_xor)
self.out.connect(self.out.N-1, obj_xor.out)
# Connecting the output bits generated from ommited cells to ground
for grounded_out_index in range(0, self.truncation_cut*2):
self.out.connect(grounded_out_index, ConstantWireValue0())

6
ariths_gen/multi_bit_circuits/multipliers/__init__.py
View File

@ -13,7 +13,7 @@ from ariths_gen.multi_bit_circuits.multipliers.dadda_multiplier import (
SignedDaddaMultiplier
)
from ariths_gen.multi_bit_circuits.multipliers.wallace_csa_multiplier import (
UnsignedWallaceCSAMultiplier,
SignedWallaceCSAMultiplier
from ariths_gen.multi_bit_circuits.multipliers.carry_save_multiplier import (
UnsignedCarrySaveMultiplier,
SignedCarrySaveMultiplier
)

285
ariths_gen/multi_bit_circuits/multipliers/carry_save_multiplier.py Normal file
View File

@ -0,0 +1,285 @@
from ariths_gen.wire_components import (
Wire,
ConstantWireValue0,
ConstantWireValue1,
Bus
)
from ariths_gen.core.arithmetic_circuits import (
ArithmeticCircuit,
MultiplierCircuit
)
from ariths_gen.one_bit_circuits.one_bit_components import (
HalfAdder,
FullAdder,
FullAdderPG
)
from ariths_gen.one_bit_circuits.logic_gates import (
AndGate,
NandGate,
OrGate,
NorGate,
XorGate,
XnorGate,
NotGate
)
from ariths_gen.multi_bit_circuits.adders import (
UnsignedCarryLookaheadAdder
)
class UnsignedCarrySaveMultiplier(MultiplierCircuit):
"""Class representing unsigned carry save array multiplier (also known as Braun multiplier).
Unsigned carry save array multiplier represents N-bit multiplier composed of
many AND gates and carry save adders to calculate partial products and
gradually sum them. As opposed to traditional architecture of an array multiplier,
the individual half/full adders are interconnected in a carry save manner to provide
smaller propagation delay.
It is composed of many logic gates and its downside is a rather big area when compared
to a regular array multiplier.
The reason for that is because the csa multiplier requires an additional vector merging
propagate adder to calculate the final product bits.
```
A3B0 A2B0 A1B0 A0B0
│ │ │ │ │ │ │ │
┌▼─▼┐ ┌▼─▼┐ ┌▼─▼┐ ┌▼─▼┐
│AND│ │AND│ │AND│ │AND│
└┬──┘ └┬──┘ └┬──┘ └─┬─┘
A3B1 │ A2B1 │ A1B1 │ A0B1 │
┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │
│AND│ │ │AND│ │ │AND│ │ │AND│ │
└┬──┘ │ └┬──┘ │ └┬──┘ │ └┬──┘ │
│ │ │ │ │ │ │ │
│ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ │
┌──┘ │ │ │ │ │ │ │
│ ┌─┤ HA │ ┌─┤ HA │ ┌─┤ HA │ │
│ │ │ │ │ │ │ │ │ │ │
│ │ └┬───┘ │ └┬───┘ │ └─┬──┘ │
A3B2 │ A2B2│ │ A1B2│ │ A0B2│ │ │
┌▼─▼┐ │┌▼─▼┐│ │┌▼─▼┐│ │┌▼─▼┐│ │ │
│AND│ ││AND││ ││AND││ ││AND││ │ │
└─┬─┘ │└─┬─┘│ │└─┬─┘│ │└─┬─┘│ │ │
│ │ │ │ │ │ │ │ │ │ │ │
│ ┌▼──▼┐ │ ┌▼──▼┐ │ ┌▼──▼┐ │ │ │
┌──┘ │ │◄┘ │ │◄┘ │ │◄┘ │ │
│ ┌─┤ FA │ ┌─┤ FA │ ┌─┤ FA │ │ │
│ │ │ │ │ │ │ │ │ │ │ │
│ │ └┬───┘ │ └┬───┘ │ └─┬──┘ │ │
A3B3 │ A2B3│ │ A1B3│ │ A0B3│ │ │ │
┌▼─▼┐ │┌▼─▼┐│ │┌▼─▼┐│ │┌▼─▼┐│ │ │ │
│AND│ ││AND││ ││AND││ ││AND││ │ │ │
└─┬─┘ │└─┬─┘│ │└─┬─┘│ │└─┬─┘│ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │ │
│ ┌▼──▼┐ │ ┌▼──▼┐ │ ┌▼──▼┐ │ │ │ │
┌─┘ │ │◄┘ │ │◄┘ │ │◄┘ │ │ │
│ ┌─┤ FA │ ┌─┤ FA │ ┌─┤ FA │ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │ │
0 0 │ │ └─┬──┘ │ └─┬──┘ │ └─┬──┘ │ │ │
│ │ │S2 │C2 │S1 │C1 │S0 │C0 │ │ │ │
┌─▼───▼───▼────▼───▼────▼───▼────▼─┐ │ │ │ │
│ Carry-propagate │ │ │ │ │
│ adder │ │ │ │ │
└┬────────┬────────┬────────┬──────┘ │ │ │ │
│ │ │ │ │ │ │ │
▼ ▼ ▼ ▼ ▼ ▼ ▼ ▼
P7 P6 P5 P4 P3 P2 P1 P0
```
Description of the __init__ method.
Args:
a (Bus): First input bus.
b (Bus): Second input bus.
prefix (str, optional): Prefix name of unsigned carry save array multiplier. Defaults to "".
name (str, optional): Name of unsigned carry save array multiplier. Defaults to "u_csamul".
unsigned_adder_class_name (str, optional): Unsigned multi bit adder used for final vector merging of sums and carries. Defaults to UnsignedCarryLookaheadAdder.
"""
def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "u_csamul", unsigned_adder_class_name: str = UnsignedCarryLookaheadAdder, **kwargs):
self.N = max(a.N, b.N)
super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, **kwargs)
# Bus sign extension in case buses have different lengths
self.a.bus_extend(N=self.N, prefix=a.prefix)
self.b.bus_extend(N=self.N, prefix=b.prefix)
# Gradual generation of partial products
for b_multiplier_index in range(self.N):
for a_multiplicand_index in range(self.N):
# AND gates generation for calculation of partial products
obj_and = AndGate(self.a.get_wire(a_multiplicand_index), self.b.get_wire(b_multiplier_index), prefix=self.prefix+"_and"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_and)
# First row contains only HAs
if b_multiplier_index == 1 and a_multiplicand_index != self.N-1:
previous_product = self.components[a_multiplicand_index + b_multiplier_index].out
obj_adder = HalfAdder(a=obj_and.out, b=previous_product, prefix=self.prefix+"_ha"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_adder)
# Rest are composed of FAs
elif b_multiplier_index > 1 and a_multiplicand_index != self.N-1:
previous_sum_wire = self.get_previous_component((self.N-1)*2-1).get_sum_wire() if a_multiplicand_index != self.N-2 else self.get_previous_component((self.N-1)*2).out
previous_carry_wire = self.get_previous_component(self.N*2-1).get_carry_wire()
obj_adder = FullAdder(a=obj_and.out, b=previous_sum_wire, c=previous_carry_wire, prefix=self.prefix+"_fa"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_adder)
# PRODUCT GENERATION
if a_multiplicand_index == 0 and b_multiplier_index == 0:
self.out.connect(a_multiplicand_index, obj_and.out)
# 1 bit multiplier case
if a_multiplicand_index == self.N-1:
self.out.connect(a_multiplicand_index+1, ConstantWireValue0())
return
elif a_multiplicand_index == 0:
self.out.connect(b_multiplier_index + a_multiplicand_index, obj_adder.get_sum_wire())
# Final addition of remaining bits using chosen unsigned multi bit adder
previous_sums = [self.get_previous_component((self.N-2-wire_id)*2).get_sum_wire() if wire_id < self.N-2 else self.get_previous_component().out if wire_id == self.N-2 else ConstantWireValue0() for wire_id in range(self.N)]
previous_carries = [self.get_previous_component((self.N-2-wire_id)*2+2).get_carry_wire() if wire_id != self.N-1 else ConstantWireValue0() for wire_id in range(self.N)]
# Obtain proper adder name with its bit width (columns bit pairs minus the first alone bit)
adder_name = unsigned_adder_class_name(a=a, b=b).prefix + str(self.N)
adder_a = Bus(prefix=f"a", wires_list=previous_sums)
adder_b = Bus(prefix=f"b", wires_list=previous_carries)
final_adder = unsigned_adder_class_name(a=adder_a, b=adder_b, prefix=self.prefix, name=adder_name, inner_component=True)
self.add_component(final_adder)
[self.out.connect(o, final_adder.out.get_wire(o-self.N), inserted_wire_desired_index=o-self.N) for o in range(self.N, len(self.out.bus))]
class SignedCarrySaveMultiplier(MultiplierCircuit):
"""Class representing signed carry save array multiplier.
Signed carry save array multiplier represents N-bit multiplier composed of
many AND/NAND gates and carry save adders to calculate partial products and
gradually sum them. As opposed to traditional architecture of an array multiplier,
the individual half/full adders are interconnected in a carry save manner to provide
smaller propagation delay.
It is composed of many logic gates and its downside is a rather big area when compared
to a regular array multiplier.
The reason for that is because the csa multiplier requires an additional vector merging
propagate adder to calculate the final product bits.
```
A3B0 A2B0 A1B0 A0B0
│ │ │ │ │ │ │ │
┌▼─▼─┐ ┌▼─▼┐ ┌▼─▼┐ ┌▼─▼┐
│NAND│ │AND│ │AND│ │AND│
└┬───┘ └┬──┘ └┬──┘ └─┬─┘
A3B1 │ A2B1 │ A1B1 │ A0B1 │
┌▼─▼─┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │
│NAND│ │ │AND│ │ │AND│ │ │AND│ │
1 └┬───┘ │ └┬──┘ │ └┬──┘ │ └┬──┘ │
│ │ │ │ │ │ │ │ │
┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ │
│ │ │ │ │ │ │ │ │
┌─┤ HA │ ┌─┤ HA │ ┌─┤ HA │ ┌─┤ HA │ │
│ │ │ │ │ │ │ │ │ │ │ │ │
│ └┬───┘ │ └┬───┘ │ └┬───┘ │ └─┬──┘ │
A3B2 │ │ A2B2│ │ A1B2│ │ A0B2│ │ │
┌▼─▼─┐│ │┌▼─▼┐│ │┌▼─▼┐│ │┌▼─▼┐│ │ │
│NAND││ ││AND││ ││AND││ ││AND││ │ │
└──┬─┘│ │└─┬─┘│ │└─┬─┘│ │└─┬─┘│ │ │
│ │ │ │ │ │ │ │ │ │ │ │ │
┌───▼┐ │ ┌▼──▼┐ │ ┌▼──▼┐ │ ┌▼──▼┐ │ │ │
│ │◄┘ │ │◄┘ │ │◄┘ │ │◄┘ │ │
┌─┤ HA │ ┌┤ FA │ ┌┤ FA │ ┌┤ FA │ │ │
│ │ │ ││ │ ││ │ ││ │ │ │
│ └┬───┘ │└┬───┘ │└┬───┘ │└─┬──┘ │ │
A3B3│ │ A3B2 │ │ A3B2 │ │ A3B2 │ │ │ │
┌▼─▼┐│ │┌▼─▼─┐│ │┌▼─▼─┐│ │┌▼─▼─┐│ │ │ │
│AND││ ││NAND││ ││NAND││ ││NAND││ │ │ │
└─┬─┘│ │└─┬──┘│ │└─┬──┘│ │└─┬──┘│ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │ │ │
┌───▼┐ │ ┌▼──▼┐ │┌▼──▼┐ │┌▼──▼┐ │ │ │ │
│ │◄┘ │ │◄─┘│ │◄─┘│ │◄─┘ │ │ │
┌─┤ HA │ ┌─┤ FA │ ┌─┤ FA │ ┌─┤ FA │ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │
1 │ └─┬──┘ │ └─┬──┘ │ └─┬──┘ │ └─┬──┘ │ │ │
│ │C3 │S2 │C2 │S1 │C1 │S0 │C0 │ │ │ │
┌─▼───▼───▼────▼───▼────▼───▼────▼─┐ │ │ │ │
│ Carry-propagate │ │ │ │ │
│ adder │ │ │ │ │
└┬────────┬────────┬────────┬──────┘ │ │ │ │
│ │ │ │ │ │ │ │
▼ ▼ ▼ ▼ ▼ ▼ ▼ ▼
P7 P6 P5 P4 P3 P2 P1 P0
```
Description of the __init__ method.
Args:
a (Bus): First input bus.
b (Bus): Second input bus.
prefix (str, optional): Prefix name of signed carry save array multiplier. Defaults to "".
name (str, optional): Name of signed carry save array multiplier. Defaults to "s_csamul".
unsigned_adder_class_name (str, optional): Unsigned multi bit adder used for final vector merging of sums and carries. Defaults to UnsignedCarryLookaheadAdder.
"""
def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "s_csamul", unsigned_adder_class_name: str = UnsignedCarryLookaheadAdder, **kwargs):
self.N = max(a.N, b.N)
super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, signed=True, **kwargs)
# Bus sign extension in case buses have different lengths
self.a.bus_extend(N=self.N, prefix=a.prefix)
self.b.bus_extend(N=self.N, prefix=b.prefix)
# Gradual generation of partial products
for b_multiplier_index in range(self.N):
for a_multiplicand_index in range(self.N):
# AND and NAND gates generation for calculation of partial products and sign extension
if (b_multiplier_index == self.N-1 and a_multiplicand_index != self.N-1) or (b_multiplier_index != self.N-1 and a_multiplicand_index == self.N-1):
obj_gate = NandGate(self.a.get_wire(a_multiplicand_index), self.b.get_wire(b_multiplier_index), prefix=self.prefix+"_nand"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_gate)
else:
obj_gate = AndGate(self.a.get_wire(a_multiplicand_index), self.b.get_wire(b_multiplier_index), prefix=self.prefix+"_and"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_gate)
# First row contains only half adders
if b_multiplier_index == 1:
previous_product = self.components[a_multiplicand_index + b_multiplier_index].out if a_multiplicand_index != self.N-1 else ConstantWireValue1()
obj_adder = HalfAdder(a=obj_gate.out, b=previous_product, prefix=self.prefix+"_ha"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_adder)
# Rest are composed of FAs and a HA
elif b_multiplier_index > 1:
previous_sum_wire = self.get_previous_component((self.N-1)*2).get_sum_wire() if a_multiplicand_index != self.N-1 else None
previous_carry_wire = self.get_previous_component(self.N*2).get_carry_wire()
# Last function block of each row is a simple HA
if a_multiplicand_index == self.N-1:
obj_adder = HalfAdder(a=obj_gate.out, b=previous_carry_wire, prefix=self.prefix+"_ha"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
# Rest are all FAs
else:
obj_adder = FullAdder(a=obj_gate.out, b=previous_sum_wire, c=previous_carry_wire, prefix=self.prefix+"_fa"+str(a_multiplicand_index)+"_"+str(b_multiplier_index))
self.add_component(obj_adder)
# PRODUCT GENERATION
if a_multiplicand_index == 0 and b_multiplier_index == 0:
self.out.connect(a_multiplicand_index, obj_gate.out)
# 1 bit multiplier case
if a_multiplicand_index == self.N-1:
obj_nor = NorGate(a=ConstantWireValue1(), b=self.get_previous_component().out, prefix=self.prefix+"_nor_zero_extend", parent_component=self)
self.add_component(obj_nor)
self.out.connect(a_multiplicand_index+1, obj_nor.out)
return
elif a_multiplicand_index == 0:
self.out.connect(b_multiplier_index + a_multiplicand_index, obj_adder.get_sum_wire())
# Final addition of remaining bits using chosen unsigned multi bit adder
previous_sums = [self.get_previous_component((self.N*2)-3-(wire_id*2)).get_sum_wire() if wire_id != self.N-1 else ConstantWireValue1() for wire_id in range(self.N)]
previous_carries = [self.get_previous_component((self.N*2)-1-(wire_id*2)).get_carry_wire() for wire_id in range(self.N)]
# Obtain proper adder name with its bit width (columns bit pairs minus the first alone bit)
adder_name = unsigned_adder_class_name(a=a, b=b).prefix + str(self.N)
adder_a = Bus(prefix=f"a", wires_list=previous_sums)
adder_b = Bus(prefix=f"b", wires_list=previous_carries)
final_adder = unsigned_adder_class_name(a=adder_a, b=adder_b, prefix=self.prefix, name=adder_name, inner_component=True)
self.add_component(final_adder)
self.out.connect_bus(connecting_bus=final_adder.out, end_connection_pos=final_adder.out.N-1, offset=(-self.N))

213
ariths_gen/multi_bit_circuits/multipliers/wallace_csa_multiplier.py
View File

@ -1,213 +0,0 @@
from ariths_gen.wire_components import (
Wire,
ConstantWireValue0,
ConstantWireValue1,
Bus
)
from ariths_gen.core.arithmetic_circuits import (
ArithmeticCircuit,
MultiplierCircuit
)
from ariths_gen.one_bit_circuits.one_bit_components import (
HalfAdder,
FullAdder,
FullAdderPG
)
from ariths_gen.one_bit_circuits.logic_gates import (
AndGate,
NandGate,
OrGate,
NorGate,
XorGate,
XnorGate,
NotGate
)
from ariths_gen.multi_bit_circuits.adders import (
CarrySaveAdderComponent,
UnsignedCarryLookaheadAdder
)
class UnsignedWallaceCSAMultiplier(MultiplierCircuit):
"""Class representing unsigned wallace multiplier composed of carry save adder components.
Unsigned wallace multiplier represents fast N-bit multiplier which utilizes
the functionality of wallace tree reduction algorithm proposed by Chris Wallace.
First partial products are calculated for each bit pair that form the partial product multiplication rows.
This implementation uses carry save adder components to efficiently implement reduction of partial products utilizing the parallelism of the carry save adders.
At last the reduced pairs are inserted into chosen multi bit unsigned adder to execute their summation and obtain the final output bits.
Wallace tree algorithm is described more in detail here:
https://en.wikipedia.org/wiki/Wallace_tree
It presents a faster version of multiplier opposed to the conventional architectures that are composed of interconnected half/full adders.
```
PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0
│ │ │ │ │ │ │ │
│ │ ┌▼──▼──▼┐ ┌▼──▼──▼┐
│ │ │ CSA │ │ CSA │
│ │ └─┬───┬─┘ └─┬───┬─┘
│ │ │c1 │s1 │c0 │s0
└┐ │ ┌──┘ └────┐ │ ┌┘
┌▼──▼──▼┐ ┌▼──▼──▼┐
│ CSA │ │ CSA │
└─┬───┬─┘ └─┬───┬─┘
│c4 │s4 ┌───────┘c3 │s3
│ └──┐ │ ┌────────┘
│ ┌▼──▼──▼┐
│ │ CSA │
│ └─┬───┬─┘
│ ┌────┘c5 │s5
│ │ ┌─────┘
┌▼──▼──▼┐
│ CSA │
└─┬───┬─┘
│c6 │s6
┌─▼───▼─┐
│ CPA │
└───┬───┘
o
```
Description of the __init__ method.
Args:
a (Bus): First input bus.
b (Bus): Second input bus.
prefix (str, optional): Prefix name of unsigned csa wallace multiplier. Defaults to "".
name (str, optional): Name of unsigned csa wallace multiplier. Defaults to "u_wallaceCSA_cla".
unsigned_adder_class_name (str, optional): Unsigned multi bit adder used to obtain final sums of products. Defaults to UnsignedCarryLookaheadAdder.
"""
def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "u_wallaceCSA_cla", unsigned_adder_class_name: str = UnsignedCarryLookaheadAdder, **kwargs):
self.N = max(a.N, b.N)
super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, **kwargs)
# Bus sign extension in case buses have different lengths
self.a.bus_extend(N=self.N, prefix=a.prefix)
self.b.bus_extend(N=self.N, prefix=b.prefix)
# Initialize all rows partial products forming AND gates matrix
self.rows = self.init_row_lengths()
# Zero extension of partial product rows
for i in range(0, len(self.rows)):
self.rows[i] = Bus(prefix=self.rows[i].prefix, wires_list=[ConstantWireValue0() for _ in range(0, i)] + self.rows[i].bus)
while len(self.rows) > 2:
# Gradual creation of unsigned csa adder components to reduce the pp rows to the total count of 2
pp_index = 0
while pp_index < len(self.rows) and (pp_index+2) < len(self.rows):
csa_reduction = CarrySaveAdderComponent(a=self.rows[pp_index], b=self.rows[pp_index+1], c=self.rows[pp_index+2], prefix=self.prefix+"_csa"+str(self.get_instance_num(cls=CarrySaveAdderComponent)), inner_component=True)
self.add_component(csa_reduction)
# 3 pp rows have been reduced to 2
[self.rows.pop(pp_index) for i in range(3)]
# Append rows of sum and carry results from csa calculation
csa_sums_N = self.out.N if csa_reduction.sum_bits.N > self.out.N-1 else csa_reduction.sum_bits.N
csa_sums = Bus(prefix=self.prefix+"_csa_s"+str(self.get_instance_num(cls=CarrySaveAdderComponent)), N=csa_sums_N)
csa_sums.connect_bus(connecting_bus=csa_reduction.out, end_connection_pos=csa_sums_N)
csa_carries_N = self.out.N if csa_reduction.carry_bits.N > self.out.N-1 else csa_reduction.carry_bits.N
csa_carries = Bus(prefix=self.prefix+"_csa_c"+str(self.get_instance_num(cls=CarrySaveAdderComponent)), N=csa_carries_N)
csa_carries.connect_bus(connecting_bus=csa_reduction.out, start_connection_pos=int(csa_reduction.out.N/2), end_connection_pos=int(csa_reduction.out.N/2)+csa_carries.N, offset=int(csa_reduction.out.N/2))
self.rows.insert(pp_index, csa_carries)
self.rows.insert(pp_index, csa_sums)
# Update of the number of pp rows
pp_index += 2
# Final addition of remaining bits using chosen unsigned multi bit adder
# Obtain proper adder name with its bit width (columns bit pairs minus the first alone bit)
adder_name = unsigned_adder_class_name(a=a, b=b).prefix + str(self.rows[0].N)
adder_a = Bus(prefix="a", N=self.rows[0].N)
adder_b = Bus(prefix="b", N=self.rows[1].N)
[adder_a.connect(w, self.rows[0].get_wire(w)) for w in range(0, self.rows[0].N)]
[adder_b.connect(w, self.rows[1].get_wire(w)) for w in range(0, self.rows[1].N)]
final_adder = unsigned_adder_class_name(a=adder_a, b=adder_b, prefix=self.prefix, name=adder_name, inner_component=True)
self.add_component(final_adder)
[self.out.connect(o, final_adder.out.get_wire(o), inserted_wire_desired_index=o) for o in range(0, final_adder.out.N-1)]
class SignedWallaceCSAMultiplier(MultiplierCircuit):
"""Class representing signed wallace multiplier composed of carry save adder components.
Signed wallace multiplier represents fast N-bit multiplier which utilizes
the functionality of wallace tree reduction algorithm proposed by Chris Wallace and uses Baugh-Wooley algorithm
to perform signed multiplication.
First partial products are calculated for each bit pair that form the partial product multiplication rows.
This implementation uses carry save adder components to efficiently implement reduction of partial products utilizing the parallelism of the carry save adders.
At last the reduced pairs are inserted into chosen multi bit unsigned adder to execute their summation and obtain the final output bits, additional XOR gate serve the necessary sign extension.
Wallace tree algorithm is described more in detail here:
https://en.wikipedia.org/wiki/Wallace_tree
It presents a faster version of multiplier opposed to the conventional architectures that are composed of interconnected half/full adders.
Description of the __init__ method.
Args:
a (Bus): First input bus.
b (Bus): Second input bus.
prefix (str, optional): Prefix name of signed csa wallace multiplier. Defaults to "".
name (str, optional): Name of signed csa wallace multiplier. Defaults to "s_wallaceCSA_cla".
unsigned_adder_class_name (str, optional): Unsigned multi bit adder used to obtain final sums of products. Defaults to UnsignedCarryLookaheadAdder.
"""
def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "s_wallaceCSA_cla", unsigned_adder_class_name: str = UnsignedCarryLookaheadAdder, **kwargs):
self.N = max(a.N, b.N)
super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, signed=True, **kwargs)
# Bus sign extension in case buses have different lengths
self.a.bus_extend(N=self.N, prefix=a.prefix)
self.b.bus_extend(N=self.N, prefix=b.prefix)
# Initialize all rows partial products forming AND gates matrix
self.rows = self.init_row_lengths()
# Zero extension of partial product rows
for i in range(0, len(self.rows)):
self.rows[i] = Bus(prefix=self.rows[i].prefix, wires_list=[ConstantWireValue0() for _ in range(0, i)] + self.rows[i].bus)
while len(self.rows) > 2:
# Gradual creation of signed csa adder components to reduce the pp rows to the total count of 2
pp_index = 0
while pp_index < len(self.rows) and (pp_index+2) < len(self.rows):
csa_reduction = CarrySaveAdderComponent(a=self.rows[pp_index], b=self.rows[pp_index+1], c=self.rows[pp_index+2], prefix=self.prefix+"_csa"+str(self.get_instance_num(cls=CarrySaveAdderComponent)), inner_component=True, signed=True)
self.add_component(csa_reduction)
# 3 pp rows have been reduced to 2
[self.rows.pop(pp_index) for i in range(3)]
# Append rows of sum and carry results from csa calculation
csa_sums_N = self.out.N if csa_reduction.sum_bits.N > self.out.N-1 else csa_reduction.sum_bits.N
csa_sums = Bus(prefix=self.prefix+"_csa_s"+str(self.get_instance_num(cls=CarrySaveAdderComponent)), N=csa_sums_N)
csa_sums.connect_bus(connecting_bus=csa_reduction.out, end_connection_pos=csa_sums_N)
csa_carries_N = self.out.N if csa_reduction.carry_bits.N > self.out.N-1 else csa_reduction.carry_bits.N
csa_carries = Bus(prefix=self.prefix+"_csa_c"+str(self.get_instance_num(cls=CarrySaveAdderComponent)), N=csa_carries_N)
csa_carries.connect_bus(connecting_bus=csa_reduction.out, start_connection_pos=int(csa_reduction.out.N/2), end_connection_pos=int(csa_reduction.out.N/2)+csa_carries.N, offset=int(csa_reduction.out.N/2))
self.rows.insert(pp_index, csa_carries)
self.rows.insert(pp_index, csa_sums)
# Update of the number of pp rows
pp_index += 2
# Final addition of remaining bits using chosen unsigned multi bit adder
# Obtain proper adder name with its bit width (columns bit pairs minus the first alone bit)
adder_name = unsigned_adder_class_name(a=a, b=b).prefix + str(self.rows[0].N)
adder_a = Bus(prefix="a", N=self.rows[0].N)
adder_b = Bus(prefix="b", N=self.rows[1].N)
[adder_a.connect(w, self.rows[0].get_wire(w)) for w in range(0, self.rows[0].N)]
[adder_b.connect(w, self.rows[1].get_wire(w)) for w in range(0, self.rows[1].N)]
final_adder = unsigned_adder_class_name(a=adder_a, b=adder_b, prefix=self.prefix, name=adder_name, inner_component=True)
self.add_component(final_adder)
[self.out.connect(o, final_adder.out.get_wire(o), inserted_wire_desired_index=o) for o in range(0, final_adder.out.N-1)]
# Final XOR to ensure proper sign extension
obj_xor = XorGate(ConstantWireValue1(), self.out.get_wire(self.out.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
self.add_component(obj_xor)
self.out.connect(self.out.N-1, obj_xor.out)

425
ariths_gen/multi_bit_circuits/multipliers/wallace_multiplier.py
View File

@ -23,6 +23,10 @@ from ariths_gen.one_bit_circuits.logic_gates import (
XnorGate,
NotGate
)
from ariths_gen.multi_bit_circuits.adders import (
CarrySaveAdderComponent,
UnsignedCarryLookaheadAdder
)
class UnsignedWallaceMultiplier(MultiplierCircuit):
@ -31,14 +35,46 @@ class UnsignedWallaceMultiplier(MultiplierCircuit):
Unsigned wallace multiplier represents fast N-bit multiplier which utilizes
the functionality of wallace tree reduction algorithm proposed by Chris Wallace.
First partial products are calculated for each bit pair that form the partial product multiplication columns.
At last the reduced pairs are inserted into chosen multi bit unsigned adder to execute their summation and obtain the final output bits.
First partial products are calculated for each bit pair that form the partial product multiplication rows/columns.
At last the reduced pairs are inserted into the chosen multi bit unsigned adder to execute their summation and obtain the final output bits.
The multiplier can be build from carry save adders or fully connected half/full adders (greater delay).
The csa implementation uses carry save adder components to efficiently implement reduction of partial products utilizing the parallelism of the carry save adders. At last the reduced pairs are inserted into chosen multi bit unsigned adder to execute their summation and obtain the final output bits. It presents a faster version of multiplier opposed to the conventional architectures that are composed of interconnected half/full adders.
Wallace tree algorithm is described more in detail here:
https://en.wikipedia.org/wiki/Wallace_tree
It presents smaller circuit in area opposed to array multiplier but is slightly bigger then dadda because of less reduction stages.
It presents a smaller circuit in area opposed to an array multiplier but is slightly bigger then dadda because of less reduction stages.
```
CSA IMPLEMENTATION:
PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0
│ │ │ │ │ │ │ │
│ │ ┌▼──▼──▼┐ ┌▼──▼──▼┐
│ │ │ CSA │ │ CSA │
│ │ └─┬───┬─┘ └─┬───┬─┘
│ │ │c1 │s1 │c0 │s0
└┐ │ ┌──┘ └────┐ │ ┌┘
┌▼──▼──▼┐ ┌▼──▼──▼┐
│ CSA │ │ CSA │
└─┬───┬─┘ └─┬───┬─┘
│c4 │s4 ┌───────┘c3 │s3
│ └──┐ │ ┌────────┘
│ ┌▼──▼──▼┐
│ │ CSA │
│ └─┬───┬─┘
│ ┌────┘c5 │s5
│ │ ┌─────┘
┌▼──▼──▼┐
│ CSA │
└─┬───┬─┘
│c6 │s6
┌─▼───▼─┐
│ CPA │
└───┬───┘
o
```
Description of the __init__ method.
Args:
@ -46,9 +82,10 @@ class UnsignedWallaceMultiplier(MultiplierCircuit):
b (Bus): Second input bus.
prefix (str, optional): Prefix name of unsigned wallace multiplier. Defaults to "".
name (str, optional): Name of unsigned wallace multiplier. Defaults to "u_wallace_cla".
use_csa (bool, optional): Choose whether to use carry save adder architecture (True) or fully interconnected half/full adders (False). Defaults to True.
unsigned_adder_class_name (str, optional): Unsigned multi bit adder used to obtain final sums of products. Defaults to UnsignedCarryLookaheadAdder.
"""
def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "u_wallace_cla", unsigned_adder_class_name: str = UnsignedCarryLookaheadAdder, **kwargs):
def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "u_wallace_cla", use_csa: bool = True, unsigned_adder_class_name: str = UnsignedCarryLookaheadAdder, **kwargs):
self.N = max(a.N, b.N)
super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, **kwargs)
@ -56,69 +93,134 @@ class UnsignedWallaceMultiplier(MultiplierCircuit):
self.a.bus_extend(N=self.N, prefix=a.prefix)
self.b.bus_extend(N=self.N, prefix=b.prefix)
# Initialize all columns partial products forming AND gates matrix
self.columns = self.init_column_heights()
# CSA IMPLEMENTATION
if use_csa is True:
# Initialize all rows partial products forming AND gates matrix
self.rows = self.init_row_lengths()
# Perform reduction until all columns have 2 or less bits in them
while not all(height <= 2 for (height, *_) in self.columns):
col = 0
while col < len(self.columns):
# If column has exactly 3 bits in height and all previous columns has maximum of 2 bits in height, combine them in a half adder
if self.get_column_height(col) == 3 and all(height <= 2 for (height, *_) in self.columns[0:col-1]):
# Add half adder and also AND gates if neccesarry (via add_column_wire invocation) into list of circuit components
obj_adder = HalfAdder(self.add_column_wire(column=col, bit=0), self.add_column_wire(column=col, bit=1), prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=HalfAdder)))
self.add_component(obj_adder)
# Zero extension of partial product rows
for i in range(0, len(self.rows)):
self.rows[i] = Bus(prefix=self.rows[i].prefix, wires_list=[ConstantWireValue0() for _ in range(0, i)] + self.rows[i].bus)
# Update the number of current and next column wires
self.update_column_heights(curr_column=col, curr_height_change=-1, next_column=col+1, next_height_change=1)
while len(self.rows) > 2:
# Gradual creation of unsigned csa adder components to reduce the pp rows to the total count of 2
pp_index = 0
while pp_index < len(self.rows) and (pp_index+2) < len(self.rows):
csa_reduction = CarrySaveAdderComponent(a=self.rows[pp_index], b=self.rows[pp_index+1], c=self.rows[pp_index+2], prefix=self.prefix+"_csa"+str(self.get_instance_num(cls=CarrySaveAdderComponent)), inner_component=True)
self.add_component(csa_reduction)
# Update current and next column wires arrangement
# add ha's generated sum to the bottom of current column
# add ha's generated cout to the top of next column
self.update_column_wires(curr_column=col, next_column=col+1, adder=self.get_previous_component(1))
# 3 pp rows have been reduced to 2
[self.rows.pop(pp_index) for i in range(3)]
# If column has more than 3 bits in height, combine them in a full adder
elif self.get_column_height(col) > 3:
# Add full adder and also AND gates if neccesarry (via add_column_wire invocation) into list of circuit components
obj_adder = FullAdder(self.add_column_wire(column=col, bit=0), self.add_column_wire(column=col, bit=1), self.add_column_wire(column=col, bit=2), prefix=self.prefix+"_fa"+str(self.get_instance_num(cls=FullAdder)))
self.add_component(obj_adder)
# Append rows of sum and carry results from csa calculation
csa_sums_N = self.out.N if csa_reduction.sum_bits.N > self.out.N-1 else csa_reduction.sum_bits.N
csa_sums = Bus(prefix=self.prefix+"_csa_s"+str(self.get_instance_num(cls=CarrySaveAdderComponent)), N=csa_sums_N)
csa_sums.connect_bus(connecting_bus=csa_reduction.out, end_connection_pos=csa_sums_N)
# Update the number of current and next column wires
self.update_column_heights(curr_column=col, curr_height_change=-2, next_column=col+1, next_height_change=1)
csa_carries_N = self.out.N if csa_reduction.carry_bits.N > self.out.N-1 else csa_reduction.carry_bits.N
csa_carries = Bus(prefix=self.prefix+"_csa_c"+str(self.get_instance_num(cls=CarrySaveAdderComponent)), N=csa_carries_N)
csa_carries.connect_bus(connecting_bus=csa_reduction.out, start_connection_pos=int(csa_reduction.out.N/2), end_connection_pos=int(csa_reduction.out.N/2)+csa_carries.N, offset=int(csa_reduction.out.N/2))
# Update current and next column wires arrangement
# add fa's generated sum to the bottom of current column
# add fa's generated cout to the top of next column
self.update_column_wires(curr_column=col, next_column=col+1, adder=self.get_previous_component(1))
col += 1
self.rows.insert(pp_index, csa_carries)
self.rows.insert(pp_index, csa_sums)
# Output generation
# First output bit from single first pp AND gate
self.out.connect(0, self.add_column_wire(column=0, bit=0))
# Final addition of remaining bits
# 1 bit multiplier case
if self.N == 1:
self.out.connect(1, ConstantWireValue0())
# 2 bit multiplier case
elif self.N == 2:
obj_ha = HalfAdder(self.add_column_wire(column=1, bit=0), self.add_column_wire(column=1, bit=1), prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=HalfAdder)))
self.add_component(obj_ha)
self.out.connect(1, obj_ha.get_sum_wire())
# Update of the number of pp rows
pp_index += 2
obj_ha = HalfAdder(self.get_previous_component().get_carry_wire(), self.add_column_wire(column=2, bit=0), prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=HalfAdder)))
self.add_component(obj_ha)
self.out.connect(2, obj_ha.get_sum_wire())
self.out.connect(3, obj_ha.get_carry_wire())
# Final addition of remaining bits using chosen unsigned multi bit adder
# Output generation
# 1 bit multiplier case
if self.N == 1:
self.out.connect(0, self.get_previous_component().out)
self.out.connect(1, ConstantWireValue0())
# 2 bit multiplier case
elif self.N == 2:
self.out.connect(0, self.components[0].out)
obj_ha = HalfAdder(a=self.components[1].out, b=self.components[2].out, prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=HalfAdder)))
self.add_component(obj_ha)
self.out.connect(1, obj_ha.get_sum_wire())
obj_ha = HalfAdder(a=self.get_previous_component().get_carry_wire(), b=self.components[3].out, prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=HalfAdder)))
self.add_component(obj_ha)
self.out.connect(2, obj_ha.get_sum_wire())
self.out.connect(3, obj_ha.get_carry_wire())
# Final addition of remaining bits using chosen unsigned multi bit adder
else:
# Obtain proper adder name with its bit width (columns bit pairs minus the first alone bit)
adder_name = unsigned_adder_class_name(a=a, b=b).prefix + str(self.rows[0].N)
adder_a = Bus(prefix="a", N=self.rows[0].N)
adder_b = Bus(prefix="b", N=self.rows[1].N)
[adder_a.connect(w, self.rows[0].get_wire(w)) for w in range(0, self.rows[0].N)]
[adder_b.connect(w, self.rows[1].get_wire(w)) for w in range(0, self.rows[1].N)]
final_adder = unsigned_adder_class_name(a=adder_a, b=adder_b, prefix=self.prefix, name=adder_name, inner_component=True)
self.add_component(final_adder)
[self.out.connect(o, final_adder.out.get_wire(o), inserted_wire_desired_index=o) for o in range(0, final_adder.out.N-1)]
# FULLY INTERCONNECTED HAs/FAs IMPLEMENTATION
else:
# Obtain proper adder name with its bit width (columns bit pairs minus the first alone bit)
adder_name = unsigned_adder_class_name(a=a, b=b).prefix + str(len(self.columns)-1)
adder_a = Bus(prefix=f"a", wires_list=[self.add_column_wire(column=col, bit=0) for col in range(1, len(self.columns))])
adder_b = Bus(prefix=f"b", wires_list=[self.add_column_wire(column=col, bit=1) for col in range(1, len(self.columns))])
final_adder = unsigned_adder_class_name(a=adder_a, b=adder_b, prefix=self.prefix, name=adder_name, inner_component=True)
self.add_component(final_adder)
# Initialize all columns partial products forming AND gates matrix
self.columns = self.init_column_heights()
[self.out.connect(o, final_adder.out.get_wire(o-1), inserted_wire_desired_index=o-1) for o in range(1, len(self.out.bus))]
# Perform reduction until all columns have 2 or less bits in them
while not all(height <= 2 for (height, *_) in self.columns):
col = 0
while col < len(self.columns):
# If column has exactly 3 bits in height and all previous columns has maximum of 2 bits in height, combine them in a half adder
if self.get_column_height(col) == 3 and all(height <= 2 for (height, *_) in self.columns[0:col-1]):
# Add half adder and also AND gates if neccesarry (via add_column_wire invocation) into list of circuit components
obj_adder = HalfAdder(self.add_column_wire(column=col, bit=0), self.add_column_wire(column=col, bit=1), prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=HalfAdder)))
self.add_component(obj_adder)
# Update the number of current and next column wires
self.update_column_heights(curr_column=col, curr_height_change=-1, next_column=col+1, next_height_change=1)
# Update current and next column wires arrangement
# add ha's generated sum to the bottom of current column
# add ha's generated cout to the top of next column
self.update_column_wires(curr_column=col, next_column=col+1, adder=self.get_previous_component(1))
# If column has more than 3 bits in height, combine them in a full adder
elif self.get_column_height(col) > 3:
# Add full adder and also AND gates if neccesarry (via add_column_wire invocation) into list of circuit components
obj_adder = FullAdder(self.add_column_wire(column=col, bit=0), self.add_column_wire(column=col, bit=1), self.add_column_wire(column=col, bit=2), prefix=self.prefix+"_fa"+str(self.get_instance_num(cls=FullAdder)))
self.add_component(obj_adder)
# Update the number of current and next column wires
self.update_column_heights(curr_column=col, curr_height_change=-2, next_column=col+1, next_height_change=1)
# Update current and next column wires arrangement
# add fa's generated sum to the bottom of current column
# add fa's generated cout to the top of next column
self.update_column_wires(curr_column=col, next_column=col+1, adder=self.get_previous_component(1))
col += 1
# Output generation
# First output bit from single first pp AND gate
self.out.connect(0, self.add_column_wire(column=0, bit=0))
# Final addition of remaining bits
# 1 bit multiplier case
if self.N == 1:
self.out.connect(1, ConstantWireValue0())
# 2 bit multiplier case
elif self.N == 2:
obj_ha = HalfAdder(self.add_column_wire(column=1, bit=0), self.add_column_wire(column=1, bit=1), prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=HalfAdder)))
self.add_component(obj_ha)
self.out.connect(1, obj_ha.get_sum_wire())
obj_ha = HalfAdder(self.get_previous_component().get_carry_wire(), self.add_column_wire(column=2, bit=0), prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=HalfAdder)))
self.add_component(obj_ha)
self.out.connect(2, obj_ha.get_sum_wire())
self.out.connect(3, obj_ha.get_carry_wire())
# Final addition of remaining bits using chosen unsigned multi bit adder
else:
# Obtain proper adder name with its bit width (columns bit pairs minus the first alone bit)
adder_name = unsigned_adder_class_name(a=a, b=b).prefix + str(len(self.columns)-1)
adder_a = Bus(prefix=f"a", wires_list=[self.add_column_wire(column=col, bit=0) for col in range(1, len(self.columns))])
adder_b = Bus(prefix=f"b", wires_list=[self.add_column_wire(column=col, bit=1) for col in range(1, len(self.columns))])
final_adder = unsigned_adder_class_name(a=adder_a, b=adder_b, prefix=self.prefix, name=adder_name, inner_component=True)
self.add_component(final_adder)
[self.out.connect(o, final_adder.out.get_wire(o-1), inserted_wire_desired_index=o-1) for o in range(1, len(self.out.bus))]
class SignedWallaceMultiplier(MultiplierCircuit):
@ -128,14 +230,13 @@ class SignedWallaceMultiplier(MultiplierCircuit):
the functionality of wallace tree reduction algorithm proposed by Chris Wallace and uses Baugh-Wooley algorithm
to perform signed multiplication.
First partial products are calculated for each bit pair that form the partial product multiplication columns.
At last the reduced pairs are inserted into chosen multi bit unsigned adder to execute their summation and obtain the final output bits,
additional XOR gate serve the necessary sign extension.
First partial products are calculated for each bit pair that form the partial product multiplication rows/columns.
The csa implementation uses carry save adder components to efficiently implement reduction of partial products utilizing the parallelism of the carry save adders. At last the reduced pairs are inserted into chosen multi bit unsigned adder to execute their summation and obtain the final output bits, additional XOR gate serves the necessary sign extension. It presents a faster version of multiplier opposed to the conventional architectures that are composed of interconnected half/full adders.
Wallace tree algorithm is described more in detail here:
https://en.wikipedia.org/wiki/Wallace_tree
It presents smaller circuit in area opposed to array multiplier but is slightly bigger then dadda because of less reduction stages.
It presents a smaller circuit in area opposed to an array multiplier but is slightly bigger then dadda because of less reduction stages.
Description of the __init__ method.
@ -144,9 +245,10 @@ class SignedWallaceMultiplier(MultiplierCircuit):
b (Bus): Second input bus.
prefix (str, optional): Prefix name of signed wallace multiplier. Defaults to "".
name (str, optional): Name of signed wallace multiplier. Defaults to "s_wallace_cla".
use_csa (bool, optional): Choose whether to use carry save adder architecture (True) or fully interconnected half/full adders (False). Defaults to True.
unsigned_adder_class_name (str, optional): Unsigned multi bit adder used to obtain final sums of products. Defaults to UnsignedCarryLookaheadAdder.
"""
def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "s_wallace_cla", unsigned_adder_class_name: str = UnsignedCarryLookaheadAdder, **kwargs):
def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "s_wallace_cla", use_csa: bool = True, unsigned_adder_class_name: str = UnsignedCarryLookaheadAdder, **kwargs):
self.N = max(a.N, b.N)
super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, signed=True, **kwargs)
@ -154,80 +256,151 @@ class SignedWallaceMultiplier(MultiplierCircuit):
self.a.bus_extend(N=self.N, prefix=a.prefix)
self.b.bus_extend(N=self.N, prefix=b.prefix)
# Initialize all columns partial products forming AND/NAND gates matrix based on Baugh-Wooley multiplication
self.columns = self.init_column_heights()
# CSA IMPLEMENTATION
if use_csa is True:
# Initialize all rows partial products forming AND gates matrix
self.rows = self.init_row_lengths()
# Not used for 1 bit multiplier
if self.N != 1:
# Adding constant wire with value 1 to achieve signedness based on Baugh-Wooley multiplication algorithm
# (adding constant value bit to last column (with one bit) to combine them in XOR gate to get the correct final multplication output bit at the end)
self.columns[self.N].insert(1, ConstantWireValue1())
self.update_column_heights(curr_column=self.N, curr_height_change=1)
# Zero extension of partial product rows
for i in range(0, len(self.rows)):
self.rows[i] = Bus(prefix=self.rows[i].prefix, wires_list=[ConstantWireValue0() for _ in range(0, i)] + self.rows[i].bus)
# Perform reduction until all columns have 2 or less bits in them
while not all(height <= 2 for (height, *_) in self.columns):
col = 0
while col < len(self.columns):
# If column has exactly 3 bits in height and all previous columns has maximum of 2 bits in height, combine them in a half adder
if self.get_column_height(col) == 3 and all(height <= 2 for (height, *_) in self.columns[0:col-1]):
# Add half adder and also AND/NAND gates if neccesarry (via add_column_wire invocation) into list of circuit components
obj_adder = HalfAdder(self.add_column_wire(column=col, bit=0), self.add_column_wire(column=col, bit=1), prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=HalfAdder)))
self.add_component(obj_adder)
while len(self.rows) > 2:
# Gradual creation of signed csa adder components to reduce the pp rows to the total count of 2
pp_index = 0
while pp_index < len(self.rows) and (pp_index+2) < len(self.rows):
csa_reduction = CarrySaveAdderComponent(a=self.rows[pp_index], b=self.rows[pp_index+1], c=self.rows[pp_index+2], prefix=self.prefix+"_csa"+str(self.get_instance_num(cls=CarrySaveAdderComponent)), inner_component=True, signed=True)
self.add_component(csa_reduction)
# Update the number of current and next column wires
self.update_column_heights(curr_column=col, curr_height_change=-1, next_column=col+1, next_height_change=1)
# 3 pp rows have been reduced to 2
[self.rows.pop(pp_index) for i in range(3)]
# Update current and next column wires arrangement
# add ha's generated sum to the bottom of current column
# add ha's generated cout to the top of next column
self.update_column_wires(curr_column=col, next_column=col+1, adder=self.get_previous_component(1))
# Append rows of sum and carry results from csa calculation
csa_sums_N = self.out.N if csa_reduction.sum_bits.N > self.out.N-1 else csa_reduction.sum_bits.N
csa_sums = Bus(prefix=self.prefix+"_csa_s"+str(self.get_instance_num(cls=CarrySaveAdderComponent)), N=csa_sums_N)
csa_sums.connect_bus(connecting_bus=csa_reduction.out, end_connection_pos=csa_sums_N)
# If column has more than 3 bits in height, combine them in a full adder
elif self.get_column_height(col) > 3:
# Add full adder and also AND/NAND gates if neccesarry (via add_column_wire invocation) into list of circuit components
obj_adder = FullAdder(self.add_column_wire(column=col, bit=0), self.add_column_wire(column=col, bit=1), self.add_column_wire(column=col, bit=2), prefix=self.prefix+"_fa"+str(self.get_instance_num(cls=FullAdder)))
self.add_component(obj_adder)
csa_carries_N = self.out.N if csa_reduction.carry_bits.N > self.out.N-1 else csa_reduction.carry_bits.N
csa_carries = Bus(prefix=self.prefix+"_csa_c"+str(self.get_instance_num(cls=CarrySaveAdderComponent)), N=csa_carries_N)
csa_carries.connect_bus(connecting_bus=csa_reduction.out, start_connection_pos=int(csa_reduction.out.N/2), end_connection_pos=int(csa_reduction.out.N/2)+csa_carries.N, offset=int(csa_reduction.out.N/2))
# Update the number of current and next column wires
self.update_column_heights(curr_column=col, curr_height_change=-2, next_column=col+1, next_height_change=1)
self.rows.insert(pp_index, csa_carries)
self.rows.insert(pp_index, csa_sums)
# Update current and next column wires arrangement
# add fa's generated sum to the bottom of current column
# add fa's generated cout to the top of next column
self.update_column_wires(curr_column=col, next_column=col+1, adder=self.get_previous_component(1))
col += 1
# Update of the number of pp rows
pp_index += 2
# Output generation
# First output bit from single first pp AND gate
self.out.connect(0, self.add_column_wire(column=0, bit=0))
# Final addition of remaining bits
# 1 bit multiplier case
if self.N == 1:
self.out.connect(1, ConstantWireValue0())
return
# 2 bit multiplier case
elif self.N == 2:
obj_ha = HalfAdder(self.add_column_wire(column=1, bit=0), self.add_column_wire(column=1, bit=1), prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=HalfAdder)))
self.add_component(obj_ha)
self.out.connect(1, obj_ha.get_sum_wire())
# Output generation
# 1 bit multiplier case
if self.N == 1:
self.out.connect(0, self.get_previous_component().out)
self.out.connect(1, ConstantWireValue0())
return
# 2 bit multiplier case
elif self.N == 2:
self.out.connect(0, self.components[0].out)
obj_ha = HalfAdder(a=self.components[1].out, b=self.components[2].out, prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=HalfAdder)))
self.add_component(obj_ha)
self.out.connect(1, obj_ha.get_sum_wire())
obj_fa = FullAdder(self.get_previous_component().get_carry_wire(), self.add_column_wire(column=2, bit=0), self.add_column_wire(column=2, bit=1), prefix=self.prefix+"_fa"+str(self.get_instance_num(cls=FullAdder)))
self.add_component(obj_fa)
self.out.connect(2, obj_fa.get_sum_wire())
self.out.connect(3, obj_fa.get_carry_wire())
obj_fa = FullAdder(a=self.get_previous_component().get_carry_wire(), b=ConstantWireValue1(), c=self.components[3].out, prefix=self.prefix+"_fa"+str(self.get_instance_num(cls=FullAdder)))
self.add_component(obj_fa)
self.out.connect(2, obj_fa.get_sum_wire())
self.out.connect(3, obj_fa.get_carry_wire())
# Final addition of remaining bits using chosen unsigned multi bit adder
# Final addition of remaining bits using chosen unsigned multi bit adder
else:
# Obtain proper adder name with its bit width (columns bit pairs minus the first alone bit)
adder_name = unsigned_adder_class_name(a=a, b=b).prefix + str(self.rows[0].N)
adder_a = Bus(prefix="a", N=self.rows[0].N)
adder_b = Bus(prefix="b", N=self.rows[1].N)
[adder_a.connect(w, self.rows[0].get_wire(w)) for w in range(0, self.rows[0].N)]
[adder_b.connect(w, self.rows[1].get_wire(w)) for w in range(0, self.rows[1].N)]
final_adder = unsigned_adder_class_name(a=adder_a, b=adder_b, prefix=self.prefix, name=adder_name, inner_component=True)
self.add_component(final_adder)
[self.out.connect(o, final_adder.out.get_wire(o), inserted_wire_desired_index=o) for o in range(0, final_adder.out.N-1)]
# Final XOR to ensure proper sign extension
obj_xor = XorGate(ConstantWireValue1(), self.out.get_wire(self.out.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
self.add_component(obj_xor)
self.out.connect(self.out.N-1, obj_xor.out)
# FULLY INTERCONNECTED HAs/FAs IMPLEMENTATION
else:
# Obtain proper adder name with its bit width (columns bit pairs minus the first alone bit)
adder_name = unsigned_adder_class_name(a=a, b=b).prefix + str(len(self.columns)-1)
adder_a = Bus(prefix=f"a", wires_list=[self.add_column_wire(column=col, bit=0) for col in range(1, len(self.columns))])
adder_b = Bus(prefix=f"b", wires_list=[self.add_column_wire(column=col, bit=1) for col in range(1, len(self.columns))])
final_adder = unsigned_adder_class_name(a=adder_a, b=adder_b, prefix=self.prefix, name=adder_name, inner_component=True)
self.add_component(final_adder)
# Initialize all columns partial products forming AND/NAND gates matrix based on Baugh-Wooley multiplication
self.columns = self.init_column_heights()
[self.out.connect(o, final_adder.out.get_wire(o-1), inserted_wire_desired_index=o-1) for o in range(1, len(self.out.bus))]
# Not used for 1 bit multiplier
if self.N != 1:
# Adding constant wire with value 1 to achieve signedness based on Baugh-Wooley multiplication algorithm
# (adding constant value bit to last column (with one bit) to combine them in XOR gate to get the correct final multplication output bit at the end)
self.columns[self.N].insert(1, ConstantWireValue1())
self.update_column_heights(curr_column=self.N, curr_height_change=1)
# Final XOR to ensure proper sign extension
obj_xor = XorGate(ConstantWireValue1(), self.out.get_wire(self.out.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
self.add_component(obj_xor)
self.out.connect(self.out.N-1, obj_xor.out)
# Perform reduction until all columns have 2 or less bits in them
while not all(height <= 2 for (height, *_) in self.columns):
col = 0
while col < len(self.columns):
# If column has exactly 3 bits in height and all previous columns has maximum of 2 bits in height, combine them in a half adder
if self.get_column_height(col) == 3 and all(height <= 2 for (height, *_) in self.columns[0:col-1]):
# Add half adder and also AND/NAND gates if neccesarry (via add_column_wire invocation) into list of circuit components
obj_adder = HalfAdder(self.add_column_wire(column=col, bit=0), self.add_column_wire(column=col, bit=1), prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=HalfAdder)))
self.add_component(obj_adder)
# Update the number of current and next column wires
self.update_column_heights(curr_column=col, curr_height_change=-1, next_column=col+1, next_height_change=1)
# Update current and next column wires arrangement
# add ha's generated sum to the bottom of current column
# add ha's generated cout to the top of next column
self.update_column_wires(curr_column=col, next_column=col+1, adder=self.get_previous_component(1))
# If column has more than 3 bits in height, combine them in a full adder
elif self.get_column_height(col) > 3:
# Add full adder and also AND/NAND gates if neccesarry (via add_column_wire invocation) into list of circuit components
obj_adder = FullAdder(self.add_column_wire(column=col, bit=0), self.add_column_wire(column=col, bit=1), self.add_column_wire(column=col, bit=2), prefix=self.prefix+"_fa"+str(self.get_instance_num(cls=FullAdder)))
self.add_component(obj_adder)
# Update the number of current and next column wires
self.update_column_heights(curr_column=col, curr_height_change=-2, next_column=col+1, next_height_change=1)
# Update current and next column wires arrangement
# add fa's generated sum to the bottom of current column
# add fa's generated cout to the top of next column
self.update_column_wires(curr_column=col, next_column=col+1, adder=self.get_previous_component(1))
col += 1
# Output generation
# First output bit from single first pp AND gate
self.out.connect(0, self.add_column_wire(column=0, bit=0))
# Final addition of remaining bits
# 1 bit multiplier case
if self.N == 1:
self.out.connect(1, ConstantWireValue0())
return
# 2 bit multiplier case
elif self.N == 2:
obj_ha = HalfAdder(self.add_column_wire(column=1, bit=0), self.add_column_wire(column=1, bit=1), prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=HalfAdder)))
self.add_component(obj_ha)
self.out.connect(1, obj_ha.get_sum_wire())
obj_fa = FullAdder(self.get_previous_component().get_carry_wire(), self.add_column_wire(column=2, bit=0), self.add_column_wire(column=2, bit=1), prefix=self.prefix+"_fa"+str(self.get_instance_num(cls=FullAdder)))
self.add_component(obj_fa)
self.out.connect(2, obj_fa.get_sum_wire())
self.out.connect(3, obj_fa.get_carry_wire())
# Final addition of remaining bits using chosen unsigned multi bit adder
else:
# Obtain proper adder name with its bit width (columns bit pairs minus the first alone bit)
adder_name = unsigned_adder_class_name(a=a, b=b).prefix + str(len(self.columns)-1)
adder_a = Bus(prefix=f"a", wires_list=[self.add_column_wire(column=col, bit=0) for col in range(1, len(self.columns))])
adder_b = Bus(prefix=f"b", wires_list=[self.add_column_wire(column=col, bit=1) for col in range(1, len(self.columns))])
final_adder = unsigned_adder_class_name(a=adder_a, b=adder_b, prefix=self.prefix, name=adder_name, inner_component=True)
self.add_component(final_adder)
[self.out.connect(o, final_adder.out.get_wire(o-1), inserted_wire_desired_index=o-1) for o in range(1, len(self.out.bus))]
# Final XOR to ensure proper sign extension
obj_xor = XorGate(ConstantWireValue1(), self.out.get_wire(self.out.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
self.add_component(obj_xor)
self.out.connect(self.out.N-1, obj_xor.out)

2
ariths_gen/pdk.py
View File

@ -6,7 +6,7 @@ directly on the level of CMOS modules.
You may add your own modules as in example in set_pdk45_library()
Please call this function before calling get_verilog_code_XXX()
Please call this function before calling get_v_code_XXX()
"""
from .one_bit_circuits import (
one_bit_components

20
ariths_gen/wire_components/buses.py
View File

@ -129,8 +129,8 @@ class Bus():
mapped_positions = [(w_id, self.bus[w_id]) for w_id in range(self.N)]
return "".join([f" {self.prefix} = 0\n"] + [f" {self.prefix} |= {w[1].return_wire_value_python_flat(offset=w[0])}" for w in mapped_positions])
def return_bus_wires_sign_extend_python(self):
"""Sign extends the bus's corresponding Python variable (object) to ensure proper Python code variable signedness.
def return_bus_wires_sign_extend_python_flat(self):
"""Sign extends the bus's corresponding Python variable (object) to ensure proper flat Python code variable signedness.
Returns:
str: Python code for sign extending the bus variable wire values.
@ -172,8 +172,8 @@ class Bus():
mapped_positions = [(w_id, self.bus[w_id]) for w_id in range(self.N)]
return "".join([f" {self.prefix} |= {w[1].return_wire_value_c_hier(offset=w[0])}" for w in mapped_positions])
def return_bus_wires_sign_extend_c(self):
"""Sign extends the bus's corresponding C variable to ensure proper C code variable signedness.
def return_bus_wires_sign_extend_c_flat(self):
"""Sign extends the bus's corresponding C variable to ensure proper flat C code variable signedness.
Returns:
str: C code for sign extending the bus variable wire values.
@ -184,6 +184,18 @@ class Bus():
else:
return ""
def return_bus_wires_sign_extend_c_hier(self):
"""Sign extends the bus's corresponding C variable to ensure proper hier C code variable signedness.
Returns:
str: C code for sign extending the bus variable wire values.
"""
if self.signed is True:
last_bus_wire = self.bus[-1]
return "".join([f" {self.prefix} |= {last_bus_wire.return_wire_value_c_hier(offset=i)}" for i in range(len(self.bus), self.c_var_size)])
else:
return ""
""" VERILOG CODE GENERATION """
def return_bus_wires_values_v_flat(self):
"""Retrieves values from bus's wires and stores them in bus's corresponding Verilog variable at proper offset bit position in the bus for flat generation.

8
ariths_gen/wire_components/wires.py
View File

@ -41,10 +41,6 @@ class Wire():
"""
if self.is_const():
return f"({self.c_const}) << {offset}\n"
# If wire is part of an input bus (where wire names are concatenated from bus prefix and their index position inside the bus in square brackets)
# then the wire value is obtained from bitwise shifting the required wire from the parent bus ('parent_bus.prefix' is the same value as 'self.prefix')
elif self.is_buswire():
return f"(({self.prefix} >> {self.index}) & 0x01) << {offset}\n"
else:
return f"(({self.name} >> 0) & 0x01) << {offset}\n"
@ -97,8 +93,6 @@ class Wire():
"""
if self.is_const():
return f"({self.c_const}) << {offset};\n"
elif self.is_buswire():
return f"(({self.prefix} >> {self.index}) & 0x01ull) << {offset};\n"
else:
return f"(({self.name} >> 0) & 0x01ull) << {offset};\n"
@ -111,6 +105,8 @@ class Wire():
Returns:
str: C code bitwise shift for storing (constant/variable) wire value at desired offset position.
"""
# If wire is part of an input bus (where wire names are concatenated from bus prefix and their index position inside the bus in square brackets)
# then the wire value is obtained from bitwise shifting the required wire from the parent bus ('parent_bus.prefix' is the same value as 'self.prefix')
if self.is_const():
return f"({self.c_const}) << {offset};\n"
else: