Vojta
813f111df7
Merge branch 'devel' of github.com:ehw-fit/ariths-gen into devel
2024-10-03 08:19:27 +02:00
Vojta
c1e8680e83
CGP with more than 26 inputs naming
2024-10-03 08:18:49 +02:00
honzastor
b87f8350fc
Added ripple borrow subtractor circuit and updated automated testing.
2024-10-01 18:42:11 +02:00
Vojta Mrazek
bc95444995
reconnected wire was not identified as a bus
2024-07-22 15:10:21 +02:00
Vojta Mrazek
04cd3e44d3
bug in cgp indexes with constant wires, they were encouted
2024-07-22 15:09:50 +02:00
Vojta Mrazek
f34471bfe3
signed version of python code
2024-07-18 13:16:15 +02:00
Vojta Mrazek
4cd1189d4a
CGP circuit accepts BUS inputs
2024-07-18 13:15:56 +02:00
Vojta Mrazek
bc0104de12
ripple cary subtractor
2024-07-09 09:22:11 +02:00
Vojta Mrazek
e41b4a2f2c
Merge branch 'devel' of github.com:ehw-fit/ariths-gen into devel
2024-07-08 11:31:30 +02:00
Vojta Mrazek
c480eeacf9
popcount parent component
2024-07-08 11:29:25 +02:00
honzastor
ce36ebf77b
Fixed hierarchical BLIF generation for popcount_compare.
2024-04-17 18:47:41 +02:00
honzastor
6003886eb7
Fixed hierarchical Verilog generation of popcount compare. BLIF probably needs a similar treatment, TBD later
2024-04-14 16:29:10 +02:00
honzastor
97e79b93da
Big code cleanup and some fixes. Hierarchical generation for popcount seems problematic. It seems bus connections are the issue.
2024-04-13 17:04:03 +02:00
honzastor
739d5fafce
Added documentation to Recursive multiplier and hopefully fixed some issues with popcount output generation.
2024-04-08 21:37:34 +02:00
Vojta Mrazek
4e331f0525
popcount with variable sizes
2024-04-08 13:48:25 +02:00
Vojta Mrazek
128b1309a1
popcount fixes
2024-04-05 09:24:03 +02:00
Vojta Mrazek
1219d7bec5
Merge branch 'popcount' into devel
2024-04-05 09:19:04 +02:00
Vojta Mrazek
2cf7b921ea
Popcount implementation
2024-04-05 08:46:02 +02:00
honzastor
da733cf44e
Added instantiation of wires and buses from inputs. Hopefully fixed now.
2024-03-28 00:06:53 +01:00
honzastor
21a6437eb8
Additional type hint fix.
2024-03-27 23:19:40 +01:00
honzastor
73101eb055
Type hint bugfix for pytest.
2024-03-27 23:10:06 +01:00
honzastor
d013a40145
Added unsigned recursive multiplier and made some bugfixes.
2024-03-27 23:00:13 +01:00
Vojta Mrazek
2e1694ccd5
popcount and compare
2024-03-22 14:19:23 +01:00
honzastor
7e1112cf81
Added individual input bus attributes to CGP Circuit objects to allow for the generation of output CGP representation.
2024-03-06 00:42:12 +01:00
Vojta Mrazek
f853a46703
CGP circuit checks
2023-04-13 12:09:07 +02:00
Vojta Mrazek
a44b0638a1
Implementation of QuAd approximate adder
2023-03-28 13:55:58 +02:00
Vojta Mrazek
a4741db191
connection checks (asserts)
2023-03-28 11:16:55 +02:00
Vojta Mrazek
44e0a920d1
MUX support of constant values
2023-03-24 12:11:42 +01:00
Vojta Mrazek
49bbc86a0f
accepts a wire as a bus
2023-03-23 13:39:32 +01:00
honzastor
7cf34d04f3
Bugfix in conditional statement.
2023-03-22 18:14:55 +01:00
honzastor
b88c502343
Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated).
2023-03-22 17:57:51 +01:00
honzastor
d52e67bb25
Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.
2023-02-24 11:13:46 +01:00
Vojta Mrazek
283f9c79f5
Merge branch 'main' into devel
2023-02-22 12:12:20 +01:00
Vojta Mrazek
6dd69c5aaa
Merge branch 'devel' of github.com:ehw-fit/ariths-gen into devel
2023-02-22 09:52:34 +01:00
Vojta Mrazek
43b3d65463
workflow modification, bus indexing
2023-02-22 09:52:06 +01:00
Vojta Mrazek
71a1d45045
string description ( #15 )
2023-02-22 09:45:14 +01:00
Vojta Mrazek
35240abc63
fix bug in python interpretation
2023-02-22 09:43:24 +01:00
Jan Klhůfek
56c86c13ca
New multipliers ( #13 )
...
* #10 CGP Circuits as inputs (#11 )
* CGP Circuits as inputs
* #10 support of signed output in general circuit
* input as output works
* output connected to input (c)
* automated verilog testing
* output rename
* Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup.
* Typos fix and code cleanup.
* Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.
* Updated automated testing scripts.
* Small bugfix in python code generation (I initially thought this line is useless).
* Updated generated circuits folder.
Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
2022-04-17 16:00:00 +02:00
Honza
b1ddc8c387
Small bugfix in python code generation (I initially thought this line is useless).
2022-04-17 13:25:10 +02:00
Honza
c0dcf42499
Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.
2022-04-17 13:04:17 +02:00
Honza
9e186d10ed
Typos fix and code cleanup.
2022-02-18 17:24:09 +01:00
Honza
6f05db002e
Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup.
2022-02-18 17:00:31 +01:00
Vojta Mrazek
3c47407f80
output rename
2022-02-07 11:29:12 +01:00
Vojta Mrazek
ee8621ef4d
output connected to input (c)
2022-02-02 12:53:18 +01:00
Vojta Mrazek
dc705106b4
input as output works
2022-02-02 11:19:32 +01:00
Vojta Mrazek
1e44c2e3dc
#10 CGP Circuits as inputs ( #11 )
...
* CGP Circuits as inputs
* #10 support of signed output in general circuit
2022-02-01 13:23:26 +01:00
Honza
13c085f169
Fixed a small bug – missing ending semicolon in generation of library desired HA/FA to Verilog. Added script for generation of AX multipliers.
2022-01-13 13:11:24 +01:00
Vojta Mrazek
d641595c3e
Support of PDK in HA and FA
2022-01-13 12:37:09 +01:00
Honza
18b44226d8
Small bugfixes and removal of redundant code.
2022-01-07 20:36:51 +01:00
Honza
d9b56e8a00
Fixed generation of unsigned variants of BAM and TM multipliers. Signed versions don't guarantee correct funcionality atm.
2022-01-06 19:23:56 +01:00
