Honza b1ddc8c387 Small bugfix in python code generation (I initially thought this line is useless).

2022-04-17 13:25:10 +02:00

..

core

Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.

2022-04-17 13:04:17 +02:00

multi_bit_circuits

Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.

2022-04-17 13:04:17 +02:00

one_bit_circuits

Fixed a small bug – missing ending semicolon in generation of library desired HA/FA to Verilog. Added script for generation of AX multipliers.

2022-01-13 13:11:24 +01:00

wire_components

Small bugfix in python code generation (I initially thought this line is useless).

2022-04-17 13:25:10 +02:00

__init__.py

Support of PDK in HA and FA

2022-01-13 12:37:09 +01:00

pdk.py

Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.

2022-04-17 13:04:17 +02:00