honzastor 21a6437eb8 Additional type hint fix.

2024-03-27 23:19:40 +01:00

..

core

Added unsigned recursive multiplier and made some bugfixes.

2024-03-27 23:00:13 +01:00

multi_bit_circuits

Additional type hint fix.

2024-03-27 23:19:40 +01:00

one_bit_circuits

connection checks (asserts)

2023-03-28 11:16:55 +02:00

wire_components

Added unsigned recursive multiplier and made some bugfixes.

2024-03-27 23:00:13 +01:00

__init__.py

Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.

2023-02-24 11:13:46 +01:00

pdk.py

Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated).

2023-03-22 17:57:51 +01:00