dissertation_thesis/ariths-gen
1
0
Fork 0
mirror of https://github.com/ehw-fit/ariths-gen.git synced 2025-04-04 06:11:41 +01:00
Code Issues Actions Packages Projects Releases Wiki Activity

Bugfix in conditional statement.

Browse Source
This commit is contained in:
honzastor 2023-03-22 18:14:55 +01:00
parent b88c502343
commit 7cf34d04f3
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
ariths_gen/core/arithmetic_circuits/general_circuit.py
View File

@ -97,12 +97,12 @@ class GeneralCircuit():
gates = []
for c in self.components:
if isinstance(c, TwoInputLogicGate):
if c.disable_generation is False and (verilog_output is False or (hasattr(self, "use_verilog_instance") and self.use_verilog_instance is False)) or hasattr(self, "use_verilog_instance") is False:
if c.disable_generation is False and (verilog_output is False or ((hasattr(self, "use_verilog_instance") and self.use_verilog_instance is False) or hasattr(self, "use_verilog_instance") is False)):
gates.append(c)
else:
# Check whether it is necessary to use gates for the Verilog component
# description (ArithsGen internally defined comp) or not (technology specific instance)
if verilog_output is False or (hasattr(c, "use_verilog_instance") and c.use_verilog_instance is False) or hasattr(c, "use_verilog_instance") is False:
if verilog_output is False or ((hasattr(c, "use_verilog_instance") and c.use_verilog_instance is False) or hasattr(c, "use_verilog_instance") is False):
gates.extend((c.get_circuit_gates(verilog_output)))
return gates