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Fixed hierarchical Verilog generation of popcount compare. BLIF probably needs a similar treatment, TBD later

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honzastor 2024-04-14 16:29:10 +02:00
parent 97e79b93da
commit 6003886eb7
8 changed files with 40 additions and 38 deletions
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27
ariths_gen/core/arithmetic_circuits/general_circuit.py
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@ -31,7 +31,7 @@ class GeneralCircuit():
attr_name = chr(97+i)
full_prefix = f"{self.prefix}_{input.prefix}" if self.inner_component else f"{input.prefix}"
if isinstance(input, Bus) or isinstance(input, Wire):
circuit_input = copy.deepcopy(input)
circuit_input = input
circuit_input.prefix = full_prefix
setattr(self, attr_name, circuit_input)
self.inputs.append(circuit_input)
@ -452,8 +452,8 @@ class GeneralCircuit():
Returns:
str: Hierarchical C code of subcomponent arithmetic circuit's wires declaration.
"""
return ";\n".join([f" {self.c_data_type} {i.prefix} = 0" for i in self.inputs]) + ";\n" + \
f" {self.c_data_type} {self.out.prefix} = 0;\n"
return "".join([f" {self.c_data_type} {i.prefix} = 0;\n" for i in self.inputs if ((isinstance(i, Wire)) or (not all((w.is_const()) or (w.parent_bus is not None and w.prefix == i.prefix) for w in i.bus)))]) + \
f" {self.c_data_type} {self.out.prefix} = 0;\n"
def get_init_c_hier(self):
"""Generates hierarchical C code initialization and assignment of corresponding arithmetic circuit's input/output wires.
@ -598,9 +598,7 @@ class GeneralCircuit():
Returns:
str: Hierarchical Verilog code of subcomponent arithmetic circuit's wires declaration.
"""
return "".join(w.get_wire_declaration_v() for w in self.inputs + [self.out]) + "\n"
#return "".join(b.get_wire_declaration_v() for b in self.inputs + [self.out] if not all((w.is_const()) or (w.parent_bus is not None and w.prefix == b.prefix) for w in b.bus)) + "\n"
return "".join(b.get_wire_declaration_v() for b in self.inputs + [self.out] if (b == self.out) or (not all((w.is_const()) or (w.parent_bus is not None and w.prefix == b.prefix) for w in b.bus)))
def get_init_v_hier(self):
"""Generates hierarchical Verilog code initialization and assignment of corresponding arithmetic circuit's input/output wires.
@ -676,16 +674,10 @@ class GeneralCircuit():
Returns:
str: Flat Blif code containing declaration of circuit's wires.
"""
if self.N == 1:
return f".inputs {' '.join([w.prefix for w in self.inputs])}\n" + \
f".outputs{self.out.get_wire_declaration_blif()}\n" + \
f".names vdd\n1\n" + \
f".names gnd\n0\n"
else:
return f".inputs{''.join([w.get_wire_declaration_blif() for w in self.inputs])}\n" + \
f".outputs{self.out.get_wire_declaration_blif()}\n" + \
f".names vdd\n1\n" + \
f".names gnd\n0\n"
return f".inputs {''.join([w.get_wire_declaration_blif() for w in self.inputs])}\n" + \
f".outputs{self.out.get_wire_declaration_blif()}\n" + \
f".names vdd\n1\n" + \
f".names gnd\n0\n"
def get_function_blif_flat(self):
"""Generates flat Blif code with invocation of subcomponents logic gates functions via their corresponding truth tables.
@ -716,6 +708,9 @@ class GeneralCircuit():
file_object.write(self.get_function_out_blif())
file_object.write(f".end\n")
# HIERARCHICAL BLIF #
def get_invocations_blif_hier(self):
"""Generates hierarchical Blif code with invocations of subcomponents function blocks.

9
ariths_gen/multi_bit_circuits/others/popcount.py
View File

@ -43,18 +43,17 @@ class UnsignedPopCount(GeneralCircuit):
#print(b_in.prefix)
#print(a, half, a.N)
for i, j in enumerate(range(half)):
b_in[i] = a[j]
b_in.connect(i, a.get_wire(j))
for i, j in enumerate(range(half, a.N)):
c_in[i] = a[j]
c_in.connect(i, a.get_wire(j))
b = create_tree(b_in, depth=depth + 1, branch = branch + "A")
c = create_tree(c_in, depth=depth + 1, branch = branch + "B")
d = self.adder(a=b, b=c, prefix = f"{self.prefix}_add{branch}_{depth}")
self.add_component(d)
return d.out
sumbus = create_tree(self.a,0, "X")
#print(sumbus)
self.out.connect_bus(sumbus)

7
ariths_gen/multi_bit_circuits/others/popcount_compare.py
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@ -38,13 +38,8 @@ class PopCountCompare(GeneralCircuit):
p2 = self.add_component(UnsignedPopCount(a=Bus(wires_list=self.b.bus, prefix=f"{prefix}_popcount2_a"),
prefix=f"{prefix}_popcount2",
inner_component=True)).out
print(p1)
#N = max(p1.N, p2.N)
#p1.bus_extend(N)
#p2.bus_extend(N)
cmp_gte_a = Bus(wires_list=p1.bus, prefix=f"{prefix}_cmp_gte_a")
cmp_gte_a.connect_bus(p1)
cmp_gte_b = Bus(wires_list=p2.bus, prefix=f"{prefix}_cmp_gte_b")
cmp_gte_b.connect_bus(p2)
red = self.add_component(UnsignedCompareGTE(cmp_gte_a, cmp_gte_b, prefix=f"{prefix}_cmp", inner_component = True))
red = self.add_component(UnsignedCompareGTE(p1, p2, prefix=f"{prefix}_cmp", inner_component = True))
self.out.connect_bus(red.out)

5
ariths_gen/wire_components/buses.py
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@ -179,7 +179,7 @@ class Bus():
"""
# Ensures correct binding between the bus wire index and the wire itself
# It is used for the case when multiple of the same wire (e.g. `ContantWireValue0()`) are present in the bus (its id would otherwise be incorrect when using `self.bus.index(_)`)
mapped_positions = [(w_id, self.bus[w_id]) for w_id in range(self.N)]
mapped_positions = [(w_id, w) for w_id, w in enumerate(self.bus) if ((w.parent_bus is None) or (w.parent_bus is not None and w.prefix != self.prefix) or (w.is_const()))]
return "".join([f" {self.prefix} |= {w[1].return_wire_value_c_hier(offset=w[0])}" for w in mapped_positions])
def return_bus_wires_sign_extend_c_flat(self):
@ -226,7 +226,7 @@ class Bus():
"""
# Ensures correct binding between the bus wire index and the wire itself
# It is used for the case when multiple of the same wire (e.g. `ContantWireValue0()`) are present in the bus (its id would otherwise be incorrect when using `self.bus.index(_)`)
mapped_positions = [(w_id, self.bus[w_id]) for w_id in range(self.N)]
mapped_positions = [(w_id, w) for w_id, w in enumerate(self.bus) if ((w.parent_bus is None) or (w.parent_bus is not None and w.prefix != self.prefix) or (w.is_const()))]
return "".join([f" assign {self.prefix}[{w[0]}] = {w[1].return_wire_value_v_hier()}" for w in mapped_positions])
def get_unique_assign_out_wires_v(self, circuit_block: object):
@ -250,7 +250,6 @@ class Bus():
"""
return f" wire [{self.N-1}:0] {self.prefix};\n"
""" BLIF CODE GENERATION """
def get_wire_declaration_blif(self, array: bool = True):
"""Declare each wire from the bus independently in Blif code representation.

16
ariths_gen/wire_components/wires.py
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@ -189,7 +189,7 @@ class Wire():
""" BLIF CODE GENERATION """
def get_declaration_blif(self, prefix: str = "", offset: int = 0, array: bool = False):
"""Wire declaration in Blif code.
"""Declaration of wire which is part of a bus in Blif code.
Declares basic wire name if wire is not part of a bus
or declares wire by an offset of its position within the bus.
@ -207,6 +207,16 @@ class Wire():
else:
return f"{self.name}"
def get_wire_declaration_blif(self):
"""Declaration of a single wire in Blif code.
Used for declaration of modul inputs.
Returns:
str: Blif code for declaration of a wire.
"""
return f" {self.prefix}\n"
def get_assign_blif(self, prefix: str, output: bool = False):
"""Assignment of wire value to another desired wire in Blif code.
@ -245,10 +255,8 @@ class Wire():
"""
if self.is_const():
return self.blif_const
elif self.parent_bus is not None and self.parent_bus.N > 1:
return self.name
else:
return self.prefix
return self.name
def __str__(self):
if self.is_const():

4
generate_mac.py
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@ -12,8 +12,8 @@ class MAC(GeneralCircuit):
assert a.N == b.N
assert r.N == 2 * a.N
self.mul = self.add_component(UnsignedArrayMultiplier(a=a, b=b, prefix=self.prefix, name=f"u_arrmul{a.N}", inner_component=True))
self.add = self.add_component(UnsignedRippleCarryAdder(a=r, b=self.mul.out, prefix=self.prefix, name=f"u_rca{r.N}", inner_component=True))
self.mul = self.add_component(UnsignedArrayMultiplier(a=Bus(wires_list=a.bus, prefix=a.prefix), b=Bus(wires_list=b.bus, prefix=b.prefix), prefix=self.prefix, name=f"u_arrmul{a.N}", inner_component=True))
self.add = self.add_component(UnsignedRippleCarryAdder(a=Bus(wires_list=r.bus, prefix=r.prefix), b=self.mul.out, prefix=self.prefix, name=f"u_rca{r.N}", inner_component=True))
self.out.connect_bus(connecting_bus=self.add.out)

4
tests/test_all.py
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@ -319,8 +319,8 @@ def test_mac():
assert a.N == b.N
assert r.N == 2 * a.N
self.mul = self.add_component(UnsignedArrayMultiplier(a=a, b=b, prefix=self.prefix, name=f"u_arrmul{a.N}", inner_component=True))
self.add = self.add_component(UnsignedRippleCarryAdder(a=r, b=self.mul.out, prefix=self.prefix, name=f"u_rca{r.N}", inner_component=True))
self.mul = self.add_component(UnsignedArrayMultiplier(a=Bus(wires_list=a.bus, prefix=a.prefix), b=Bus(wires_list=b.bus, prefix=b.prefix), prefix=self.prefix, name=f"u_arrmul{a.N}", inner_component=True))
self.add = self.add_component(UnsignedRippleCarryAdder(a=Bus(wires_list=r.bus, prefix=r.prefix), b=self.mul.out, prefix=self.prefix, name=f"u_rca{r.N}", inner_component=True))
self.out.connect_bus(connecting_bus=self.add.out)
# usage

6
tests/test_popcount_compare.py
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@ -173,3 +173,9 @@ def test_popcountcompare_small2_cgp():
#expected = np.sum(r, axis=1)
np.testing.assert_array_equal(v, expected)
if __name__ == "__main__":
#test_popcountcompare_small()
#test_popcountcompare_same()
#test_popcountcompare_small2()
#test_popcountcompare_small2_cgp()