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Implementation of QuAd approximate adder
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Vojta Mrazek
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commit
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from .quad import QuAdder
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192
ariths_gen/multi_bit_circuits/approximate_adders/quad.py
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192
ariths_gen/multi_bit_circuits/approximate_adders/quad.py
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"""
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Implementation of QuAdder
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For more information, see:
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M. A. Hanif, R. Hafiz, O. Hasan and M. Shafique, "QuAd: Design and analysis of Quality-area optimal Low-Latency approximate Adders," 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, TX, USA, 2017, pp. 1-6, doi: 10.1145/3061639.3062306.
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"""
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from ...wire_components import (
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Wire,
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ConstantWireValue0,
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ConstantWireValue1,
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Bus
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)
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from ariths_gen.core.arithmetic_circuits import (
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ArithmeticCircuit,
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MultiplierCircuit
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)
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from ariths_gen.one_bit_circuits.one_bit_components import (
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HalfAdder,
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FullAdder
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)
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from ariths_gen.one_bit_circuits.logic_gates import (
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AndGate,
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NandGate,
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OrGate,
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NorGate,
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XorGate,
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XnorGate,
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NotGate
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)
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from ariths_gen.multi_bit_circuits.adders.ripple_carry_adder import UnsignedRippleCarryAdder
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import warnings
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class QuAdder(ArithmeticCircuit):
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"""
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Implementation of QuAd
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https://ieeexplore.ieee.org/document/8060326
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The implementation is inspired by Matlab code from the authors of the paper:
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```matlab
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temp_count=1;
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for iij=1:length(R_vect)
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fprintf(fileID,['wire [' num2str(R_vect(iij)+P_vect(iij)) ':0] temp' num2str(temp_count) ';\n']);
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temp_count=temp_count + 1;
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end
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temp_count=1;
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for iiij=1:length(R_vect)
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if (sum(R_vect(1:iiij))+P_vect(1)-1) == (sum(R_vect(1:iiij))+P_vect(1)-R_vect(iiij)-P_vect(iiij))
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fprintf(fileID,['aassign temp' num2str(temp_count) '[' num2str(R_vect(iiij)+P_vect(iiij)) ':0] = in1[' num2str(sum(R_vect(1:iiij))+P_vect(1)-1) '] + in2[' num2str(sum(R_vect(1:iiij))+P_vect(1)-1) '];\n']);
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else
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disp(R_vect(1:iiij))
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fprintf(fileID,['bassign temp' num2str(temp_count) '[' num2str(R_vect(iiij)+P_vect(iiij)) ':0] = in1[' num2str(sum(R_vect(1:iiij))+P_vect(1)-1) ':' num2str(sum(R_vect(1:iiij))+P_vect(1)-R_vect(iiij)-P_vect(iiij)) '] + in2[' num2str(sum(R_vect(1:iiij))+P_vect(1)-1) ':' num2str(sum(R_vect(1:iiij))+P_vect(1)-R_vect(iiij)-P_vect(iiij)) '];\n']);
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end
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temp_count=temp_count+1;
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end
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statement='};\n';
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temp_count=1;
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for iiij=1:length(R_vect)
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if iiij ~= length(R_vect)
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if (R_vect(iiij)==1)
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statement = [', temp' num2str(temp_count) '[' num2str(R_vect(iiij)+P_vect(iiij)-1) '] ' statement];
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else
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statement = [', temp' num2str(temp_count) '[' num2str(R_vect(iiij)+P_vect(iiij)-1) ':' num2str(P_vect(iiij)) '] ' statement];
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end
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else
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statement = ['assign res[' num2str(N) ':0] =' '{ temp' num2str(temp_count) '[' num2str(R_vect(iiij)+P_vect(iiij)) ':' num2str(P_vect(iiij)) '] ' statement];
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end
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temp_count=temp_count+1;
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end
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```
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"""
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def log(self, *args):
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if self.use_log:
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print(*args)
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def __init__(self, a, b, R, P, prefix, name="quad", adder_type=None, use_log=False, **kwargs):
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"""
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:param a: Bus first input
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:param b: Bus second input
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:param R: list of integers, defines the resultant bits of all the sub-adders (the first index specifies the resultant bits of sub-adder 1 and so on)
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:param P: list of integers, defines the prediction bits of all the sub-adders (again the first index specifies the prediction bits of sub-adder 1 and so on)
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"""
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if not adder_type:
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adder_type = UnsignedRippleCarryAdder
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# Assumptions checks
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assert len(R) == len(P), "R and P must have the same length"
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print([P[i] < P[i-1] + R[i-1] for i in range(1, len(P))])
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assert all([P[i] < P[i-1] + R[i-1] for i in range(1, len(P))]
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), "Pi must be lower than Pi-1 + Ri-1"
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assert sum(R) == a.N, "Sum of R must be equal to number of bits"
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self.use_log = use_log
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self.N = max(a.N, b.N)
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super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N+1, **kwargs)
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# Bus sign extension in case buses have different lengths
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self.a.bus_extend(N=self.N, prefix=a.prefix)
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self.b.bus_extend(N=self.N, prefix=b.prefix)
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#warnings.warn("QuAdder is not tested yet")
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# Connect all outputs to zero
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for i in range(self.N+1):
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self.out[i] = ConstantWireValue0()
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# Declaration of temporary wires (just for debug purposes)
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temp_count = 0
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for iiij in range(0, len(R)):
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self.log('wire [' + str(R[iiij]+P[iiij]) +
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':0] temp' + str(temp_count) + ';')
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temp_count = temp_count + 1
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def bus_subconnect(out_bus, in_bus, out_indexes, in_indexes):
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out_indexes = list(out_indexes)
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in_indexes = list(in_indexes)
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assert len(out_indexes) == len(in_indexes)
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for i, j in zip(out_indexes, in_indexes):
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if j >= in_bus.N:
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out_bus[i] = ConstantWireValue0() # unsigned extension
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else:
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out_bus.connect(i, in_bus.get_wire(j)) # [i] = in_bus[j]
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# Connection of adders
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temp_count = 0
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temp_bus = []
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for iiij in range(0, len(R)):
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# Former verilog output
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self.log("assign temp{}[{}:0] = in1[{}:{}] + in2[{}:{}];".format(
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temp_count,
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R[iiij]+P[iiij],
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sum(R[0:iiij + 1]) + P[0]-1,
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sum(R[0:iiij + 1]) + P[0]-R[iiij]-P[iiij],
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sum(R[0:iiij + 1]) + P[0]-1,
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sum(R[0:iiij + 1]) + P[0]-R[iiij]-P[iiij]
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))
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a1 = Bus(f"{prefix}_temp_{temp_count}_a", R[iiij]+P[iiij])
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b1 = Bus(f"{prefix}_temp_{temp_count}_b", R[iiij]+P[iiij])
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bus_subconnect(b1, self.b,
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range(R[iiij]+P[iiij]),
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range(sum(R[0:iiij + 1])+P[0]-R[iiij]-P[iiij], sum(R[0:iiij + 1])+P[0]))
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bus_subconnect(a1, self.a,
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range(R[iiij]+P[iiij]),
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range(sum(R[0:iiij + 1])+P[0]-R[iiij]-P[iiij], sum(R[0:iiij + 1])+P[0]))
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temp_bus.append(self.add_component(
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adder_type(a1, b1, prefix=f"{prefix}_add_{temp_count}")
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))
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temp_count = temp_count+1
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# Final connection
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temp_count = 0
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statement = "}"
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wire_id = 0
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for iiij in range(0, len(R)):
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if iiij != len(R) - 1:
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if R[iiij] == 1:
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statement = ', temp{}[{}]'.format(
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temp_count, R[iiij]+P[iiij] - 1) + statement
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else:
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statement = ', temp{}[{}:{}]'.format(
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temp_count, R[iiij]+P[iiij] - 1, P[iiij]) + statement
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else:
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statement = 'assign res[' + str(self.N) + ':0] =' + '{ temp' + str(
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temp_count) + '[' + str(R[iiij]+P[iiij]) + ':' + str(P[iiij]) + '] ' + statement
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self.log(statement)
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for i in range(P[iiij], R[iiij]+P[iiij]):
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self.log(temp_count, i, wire_id, temp_bus[temp_count].out[i])
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self.out[wire_id] = temp_bus[temp_count].out[i]
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wire_id += 1
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temp_count = temp_count+1
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# Last carry (MSB)
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self.out[wire_id] = temp_bus[temp_count - 1].out[R[iiij]+P[iiij]]
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79
generate_quad_lib.py
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79
generate_quad_lib.py
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"""
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This script generate the library of all possible QuAdders with N bits.
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Note that the adders are not Pareto-optimal.
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"""
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from ariths_gen.core.arithmetic_circuits.arithmetic_circuit import ArithmeticCircuit
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from ariths_gen.core.arithmetic_circuits import GeneralCircuit
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from ariths_gen.wire_components import Bus, Wire
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from ariths_gen.multi_bit_circuits.adders import UnsignedRippleCarryAdder
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from ariths_gen.multi_bit_circuits.approximate_adders import QuAdder
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from ariths_gen.multi_bit_circuits.multipliers import UnsignedArrayMultiplier, UnsignedDaddaMultiplier
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import os, sys
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import numpy as np
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import itertools
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if __name__ == "__main__":
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directory = f"lib_quad/lib_quad{N}"
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os.makedirs(directory, exist_ok=True)
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# generate the C code
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cfile = open(f"{directory}/lib_quad_{N}.c", "w")
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hfile = open(f"{directory}/lib_quad_{N}.h", "w")
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hfile.write("#include <stdint.h>\n")
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data = {}
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# verilog code is zipped
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import zipfile
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vfile = zipfile.ZipFile(file=f"{directory}/lib_quad_{N}.zip", mode="w", compression=zipfile.ZIP_DEFLATED)
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cnt = 0
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N = 8
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# up to 3 stages
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for n in [1, 2, 3]:
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Rall = list(itertools.product(range(1, N + 1), repeat=n))
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for R in Rall:
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# skip invalid R
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if sum(R) != N:
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continue
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for P in itertools.product(range(0, N + 1), repeat=n):
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# test the condition from the paper
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if not all([P[i] < P[i-1] + R[i-1] for i in range(1, len(P))]):
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continue
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print(cnt, R, P) # print the current configuration
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prefix = f"quad_{N}"
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name = "r_{}_p_{}".format("_".join([str(r) for r in R]), "_".join([str(p) for p in P]))
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try:
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c = QuAdder(Bus("a", N), Bus("b", N), R = R, P=P, name=name, prefix=prefix, use_log=False)
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c.get_c_code_flat(file_object=cfile)
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vf = vfile.open(f"{prefix}_{name}.v", "w")
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# convert byte file vf to text file
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import io
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vt = io.TextIOWrapper(vf, encoding="utf-8")
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c.get_v_code_flat(file_object=vt)
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vt.close()
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cfile.write("\n\n")
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hfile.write(f"uint64_t {prefix}_{name}(uint64_t a, uint64_t b);")
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data[f"{name}_{prefix}"] = {
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"bw": N,
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"cfun": f"{prefix}_{name}",
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"verilog": f"{prefix}_{name}.v",
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"verilog_entity": f"{prefix}_{name}",
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"quad_r" : R,
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"quad_p" : P,
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}
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cnt += 1
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except IOError as e:
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print(R, P, e)
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# store the metadata
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import json, gzip
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json.dump(data, gzip.open(f"{directory}/lib_quad_{N}.json.gz", "wt"), indent=4)
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26
tests/test_ax.py
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tests/test_ax.py
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"""
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Testing the QuAdder
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"""
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from ariths_gen.core.arithmetic_circuits.arithmetic_circuit import ArithmeticCircuit
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from ariths_gen.core.arithmetic_circuits import GeneralCircuit
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from ariths_gen.wire_components import Bus, Wire
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from ariths_gen.multi_bit_circuits.adders import UnsignedRippleCarryAdder
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from ariths_gen.multi_bit_circuits.approximate_adders import QuAdder
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from ariths_gen.multi_bit_circuits.multipliers import UnsignedArrayMultiplier, UnsignedDaddaMultiplier
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import os, sys
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import numpy as np
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import itertools
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def test_quadder():
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c = QuAdder(Bus("a", 8), Bus("b", 8), R = [4, 2, 2], P=[0, 2, 2], prefix="quad")
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c.get_v_code_hier(file_object=sys.stdout)
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x = np.arange(0, 256).reshape(-1, 1)
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y = np.arange(0, 256).reshape(1, -1)
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r = c(x, y)
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r2 = x + y
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assert np.abs(r - r2).max() == 64
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np.testing.assert_equal(np.abs(r - r2).mean(), 7.5)
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