dissertation_thesis/ariths-gen
1
0
Fork 0
mirror of https://github.com/ehw-fit/ariths-gen.git synced 2025-04-04 06:11:41 +01:00
Code Issues Actions Packages Projects Releases Wiki Activity

MUX support of constant values

Browse Source
This commit is contained in:
Vojta Mrazek 2023-03-24 12:11:42 +01:00
parent 49bbc86a0f
commit 44e0a920d1
1 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py
View File

@ -311,13 +311,14 @@ class TwoOneMultiplexer(ThreeInputOneBitCircuit):
if not self.use_verilog_instance:
return super().get_init_v_flat()
# TODO - replace by one verilog_instance_format!
neg_out_w_name = f"neg_{self.out.get_wire(0).name}"
return f" wire {neg_out_w_name};\n " + self.use_verilog_instance.format(
**{
"unit": self.prefix,
"wirea": self.a.name,
"wireb": self.b.name,
"wires": self.c.name,
"wirea": f"1'b{self.a.value}" if self.a.is_const() else self.a.name,
"wireb": f"1'b{self.b.value}" if self.b.is_const() else self.b.name,
"wires": f"1'b{self.c.value}" if self.c.is_const() else self.c.name,
"wirey": neg_out_w_name,
}) + ";\n" + f" assign {self.out.get_wire(0).name} = ~{neg_out_w_name};\n"