185 Commits

Author SHA1 Message Date
Vojta Mrazek
a6060fa2a8
Update setup.cfg
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2024-12-13 12:51:46 +01:00
Vojta Mrazek
7f17461d73
Update setup.cfg 2024-12-13 12:44:51 +01:00
Vojta Mrazek
adfcfc51d0
Create python-publish.yml 2024-12-13 12:33:27 +01:00
Jan Klhůfek
63a11f244c
Merge pull request #27 from ehw-fit/devel
Devel
2024-10-03 12:39:02 +02:00
Vojta
616efb25db workflow documentation 2024-10-03 08:20:24 +02:00
Vojta
813f111df7 Merge branch 'devel' of github.com:ehw-fit/ariths-gen into devel 2024-10-03 08:19:27 +02:00
Vojta
c1e8680e83 CGP with more than 26 inputs naming 2024-10-03 08:18:49 +02:00
Vojta Mrazek
397876b265
Merge pull request #26 from ehw-fit/devel
Merge Devel into Main
2024-10-02 21:30:58 +02:00
honzastor
e804265a7b Updated git actions. 2024-10-02 14:56:52 +02:00
honzastor
03212a62f5 Actions fix 2024-10-01 18:47:24 +02:00
honzastor
b87f8350fc Added ripple borrow subtractor circuit and updated automated testing. 2024-10-01 18:42:11 +02:00
Vojta Mrazek
bc95444995 reconnected wire was not identified as a bus 2024-07-22 15:10:21 +02:00
Vojta Mrazek
04cd3e44d3 bug in cgp indexes with constant wires, they were encouted 2024-07-22 15:09:50 +02:00
Vojta Mrazek
f34471bfe3 signed version of python code 2024-07-18 13:16:15 +02:00
Vojta Mrazek
4cd1189d4a CGP circuit accepts BUS inputs 2024-07-18 13:15:56 +02:00
Vojta Mrazek
bc0104de12 ripple cary subtractor 2024-07-09 09:22:11 +02:00
Vojta Mrazek
e41b4a2f2c Merge branch 'devel' of github.com:ehw-fit/ariths-gen into devel 2024-07-08 11:31:30 +02:00
Vojta Mrazek
c480eeacf9 popcount parent component 2024-07-08 11:29:25 +02:00
honzastor
ce36ebf77b Fixed hierarchical BLIF generation for popcount_compare. 2024-04-17 18:47:41 +02:00
honzastor
f4b816fc09 Fix for workflow tests 2024-04-14 16:36:45 +02:00
honzastor
6003886eb7 Fixed hierarchical Verilog generation of popcount compare. BLIF probably needs a similar treatment, TBD later 2024-04-14 16:29:10 +02:00
honzastor
97e79b93da Big code cleanup and some fixes. Hierarchical generation for popcount seems problematic. It seems bus connections are the issue. 2024-04-13 17:04:03 +02:00
honzastor
739d5fafce Added documentation to Recursive multiplier and hopefully fixed some issues with popcount output generation. 2024-04-08 21:37:34 +02:00
Vojta Mrazek
4e331f0525 popcount with variable sizes 2024-04-08 13:48:25 +02:00
Jan Klhůfek
211dd49fb5
Merge pull request #25 from ehw-fit/popcount
Popcount
2024-04-05 12:40:39 +02:00
Vojta Mrazek
0180735dd5 workflow to node.js 20 2024-04-05 11:27:41 +02:00
Vojta Mrazek
84a41ad93c test unique #21 2024-04-05 11:25:37 +02:00
Vojta Mrazek
77724ad115 workflow update 2024-04-05 11:21:42 +02:00
Vojta Mrazek
128b1309a1 popcount fixes 2024-04-05 09:24:03 +02:00
Vojta Mrazek
8468c5b8fd
Merge pull request #24 from ehw-fit/devel
Devel merge to popcount
2024-04-05 09:19:26 +02:00
Vojta Mrazek
1219d7bec5
Merge branch 'popcount' into devel 2024-04-05 09:19:04 +02:00
Vojta Mrazek
2cf7b921ea Popcount implementation 2024-04-05 08:46:02 +02:00
honzastor
da733cf44e Added instantiation of wires and buses from inputs. Hopefully fixed now. 2024-03-28 00:06:53 +01:00
honzastor
cd3441ff00 Removed error tests from overall testing. 2024-03-27 23:44:34 +01:00
honzastor
21a6437eb8 Additional type hint fix. 2024-03-27 23:19:40 +01:00
honzastor
73101eb055 Type hint bugfix for pytest. 2024-03-27 23:10:06 +01:00
honzastor
d013a40145 Added unsigned recursive multiplier and made some bugfixes. 2024-03-27 23:00:13 +01:00
Vojta Mrazek
2e1694ccd5 popcount and compare 2024-03-22 14:19:23 +01:00
honzastor
7e1112cf81 Added individual input bus attributes to CGP Circuit objects to allow for the generation of output CGP representation. 2024-03-06 00:42:12 +01:00
Vojta Mrazek
f853a46703 CGP circuit checks 2023-04-13 12:09:07 +02:00
Vojta Mrazek
a44b0638a1 Implementation of QuAd approximate adder 2023-03-28 13:55:58 +02:00
Vojta Mrazek
a4741db191 connection checks (asserts) 2023-03-28 11:16:55 +02:00
Vojta Mrazek
44e0a920d1 MUX support of constant values 2023-03-24 12:11:42 +01:00
Vojta Mrazek
49bbc86a0f accepts a wire as a bus 2023-03-23 13:39:32 +01:00
Vojta Mrazek
363e402e16 workflow: docs 2023-03-23 08:00:37 +01:00
Vojta Mrazek
d16ab17512
Merge pull request #20 from ehw-fit/main
Main to devel
2023-03-23 07:53:54 +01:00
honzastor
7cf34d04f3 Bugfix in conditional statement. 2023-03-22 18:14:55 +01:00
honzastor
b88c502343 Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated). 2023-03-22 17:57:51 +01:00
Jan Klhůfek
cf747918bf
Merge pull request #19 from ehw-fit/devel 2023-02-24 14:12:40 +01:00
Vojta Mrazek
bb4c6d35a7 page deploy 2023-02-24 13:41:36 +01:00