Lukas Plevac
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e662c52e75
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Static write FA to PGAdder
BUILD / test (push) Successful in 1m51s
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2025-01-19 19:10:26 +01:00 |
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Lukas Plevac
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6c8c791fb5
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Code generation fix
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2025-01-19 18:34:41 +01:00 |
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db25df54cd
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unexpected keyword argument 'parent_component'
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2025-01-15 19:33:13 +01:00 |
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cf4a6ccc52
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Incorect FA instance create
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2025-01-15 19:31:12 +01:00 |
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aefc20693a
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Full adder missing import
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2025-01-15 19:28:29 +01:00 |
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395750eac5
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Imprt missing full adder
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2025-01-15 19:23:47 +01:00 |
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d0501238f8
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GCP PGA ADDER
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2025-01-06 13:03:21 +01:00 |
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Lukas Plevac
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c9c99fbb11
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Optimalize MUX
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2024-11-16 20:54:41 +01:00 |
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c476479827
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Fix mux with wrong gate ordering
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CodeQL / Analyze (python) (push) Failing after 39s
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2024-11-14 15:15:17 +01:00 |
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Lukas Plevac
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4eb65e10da
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All working muls and adders
BUILD / Python ${{ matrix.python-version }} test (3.11) (push) Has been cancelled
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CodeQL / Analyze (python) (push) Failing after 45s
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2024-10-17 19:11:02 +02:00 |
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Lukas Plevac
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09a12f3df7
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Fully working xorGateComponent
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2024-10-10 13:33:09 +02:00 |
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Lukas Plevac
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c61244c966
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Fixed RCA by test
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2024-10-08 14:28:38 +02:00 |
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Lukas Plevac
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6132c3c449
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Optimalized MAJ implementation for adders
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2024-10-08 13:39:48 +02:00 |
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Lukas Plevac
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ad9f62e3de
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Added support for MIG excluded xor and xnor gate
CodeQL / Analyze (python) (push) Waiting to run
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2024-10-07 15:19:55 +02:00 |
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honzastor
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ce36ebf77b
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Fixed hierarchical BLIF generation for popcount_compare.
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2024-04-17 18:47:41 +02:00 |
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Vojta Mrazek
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2cf7b921ea
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Popcount implementation
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2024-04-05 08:46:02 +02:00 |
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Vojta Mrazek
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a4741db191
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connection checks (asserts)
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2023-03-28 11:16:55 +02:00 |
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Vojta Mrazek
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44e0a920d1
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MUX support of constant values
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2023-03-24 12:11:42 +01:00 |
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honzastor
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b88c502343
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Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated).
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2023-03-22 17:57:51 +01:00 |
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honzastor
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d52e67bb25
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Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.
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2023-02-24 11:13:46 +01:00 |
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Honza
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13c085f169
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Fixed a small bug – missing ending semicolon in generation of library desired HA/FA to Verilog. Added script for generation of AX multipliers.
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2022-01-13 13:11:24 +01:00 |
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Vojta Mrazek
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d641595c3e
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Support of PDK in HA and FA
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2022-01-13 12:37:09 +01:00 |
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honzastor
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670ba45ee5
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Generated sample circuits for various representations. Updated C code circuits testing simulations and did some cleanup.
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2021-04-23 02:44:14 +02:00 |
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honzastor
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ad1c6ec557
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Updated circuits documentation.
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2021-04-21 13:42:07 +02:00 |
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honzastor
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8e950fc51f
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Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits.
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2021-04-21 11:33:07 +02:00 |
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honzastor
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068def0226
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Added documentation of classes methods.
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2021-04-06 01:39:11 +02:00 |
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honzastor
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a336a683e7
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Added some code documentation and updated git action to generate it.
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2021-03-31 04:40:54 +02:00 |
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Jan Klhůfek
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82d2d02ef5
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Delete ariths_gen/one_bit_circuits/logic_gates/__pycache__ directory
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2021-03-30 03:13:15 +02:00 |
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Jan Klhůfek
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debef13087
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Delete ariths_gen/one_bit_circuits/one_bit_components/__pycache__ directory
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2021-03-30 03:13:04 +02:00 |
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Jan Klhůfek
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1e2ae53df5
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Delete ariths_gen/one_bit_circuits/__pycache__ directory
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2021-03-30 03:11:57 +02:00 |
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honzastor
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69e2514852
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Updated project's structure. Renamed class names to properly fit Python naming convention. TBD: proper documentation.
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2021-03-30 03:04:48 +02:00 |
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