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Author SHA1 Message Date
Jan Klhůfek
6bbe9eb253
Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers. (#18) 2023-02-24 13:34:35 +01:00
honzastor
d52e67bb25 Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers. 2023-02-24 11:13:46 +01:00
Jan Klhůfek
2d7e157453
Merge pull request #17 from ehw-fit/devel 2023-02-22 18:59:31 +01:00
Vojta Mrazek
283f9c79f5
Merge branch 'main' into devel 2023-02-22 12:12:20 +01:00
Vojta Mrazek
d022195e48
Workflow (#16) 
* workflow

* workflow

* workflow
 2023-02-22 12:08:21 +01:00
Vojta Mrazek
da4347148c workflow python 3.6 version 2023-02-22 10:00:32 +01:00
Vojta Mrazek
60c4d3d24e workflow python 3.6 version 2023-02-22 09:55:19 +01:00
Vojta Mrazek
6dd69c5aaa Merge branch 'devel' of github.com:ehw-fit/ariths-gen into devel 2023-02-22 09:52:34 +01:00
Vojta Mrazek
43b3d65463 workflow modification, bus indexing 2023-02-22 09:52:06 +01:00
Vojta Mrazek
71a1d45045
string description (#15) 2023-02-22 09:45:14 +01:00
Vojta Mrazek
35240abc63 fix bug in python interpretation 2023-02-22 09:43:24 +01:00
Vojta Mrazek
a4a48dea57
Create codeql-analysis.yml (#14) 2022-05-26 10:08:35 +02:00
Jan Klhůfek
56c86c13ca
New multipliers (#13) 
* #10 CGP Circuits as inputs (#11)

* CGP Circuits as inputs

* #10 support of signed output in general circuit

* input as output works

* output connected to input (c)

* automated verilog testing

* output rename

* Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup.

* Typos fix and code cleanup.

* Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.

* Updated automated testing scripts.

* Small bugfix in python code generation (I initially thought this line is useless).

* Updated generated circuits folder.

Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
 2022-04-17 16:00:00 +02:00
Honza
f17e87738e Updated generated circuits folder. 2022-04-17 13:41:32 +02:00
Honza
b1ddc8c387 Small bugfix in python code generation (I initially thought this line is useless). 2022-04-17 13:25:10 +02:00
Honza
5d2f4e07e7 Updated automated testing scripts. 2022-04-17 13:06:46 +02:00
Honza
c0dcf42499 Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats. 2022-04-17 13:04:17 +02:00
Jan Klhůfek
5475e3aa75
Added ArXiv badge and paper reference (#12) 
* Update README.md

* Update README.md

* Update README.md

* Update README.md
 2022-03-25 07:19:38 +01:00
Honza
9e186d10ed Typos fix and code cleanup. 2022-02-18 17:24:09 +01:00
Honza
6f05db002e Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup. 2022-02-18 17:00:31 +01:00
Vojta Mrazek
3c47407f80 output rename 2022-02-07 11:29:12 +01:00
Vojta Mrazek
1c2efef024 automated verilog testing 2022-02-02 13:19:54 +01:00
Vojta Mrazek
ee8621ef4d output connected to input (c) 2022-02-02 12:53:18 +01:00
Vojta Mrazek
dc705106b4 input as output works 2022-02-02 11:19:32 +01:00
Vojta Mrazek
1e44c2e3dc
#10 CGP Circuits as inputs (#11) 
* CGP Circuits as inputs

* #10 support of signed output in general circuit
 2022-02-01 13:23:26 +01:00
Vojta Mrazek
d445f9e3c7
Merge pull request #9 from ehw-fit/devel 
Develop
v1.0 		2022-01-13 16:16:02 +01:00
Vojta Mrazek
5646334b7f workflow axmult typo 2022-01-13 16:11:48 +01:00
Vojta Mrazek
aeacd72d24 Readme, axmults in workflow 2022-01-13 16:10:51 +01:00
Honza
13c085f169 Fixed a small bug – missing ending semicolon in generation of library desired HA/FA to Verilog. Added script for generation of AX multipliers. 2022-01-13 13:11:24 +01:00
Vojta Mrazek
d641595c3e Support of PDK in HA and FA 2022-01-13 12:37:09 +01:00
Honza
18b44226d8 Small bugfixes and removal of redundant code. 2022-01-07 20:36:51 +01:00
Honza
d9b56e8a00 Fixed generation of unsigned variants of BAM and TM multipliers. Signed versions don't guarantee correct funcionality atm. 2022-01-06 19:23:56 +01:00
Honza
2075c0edf5 Another fix 2022-01-06 06:46:11 +01:00
Honza
b66c1bdfe0 Import fix 2022-01-06 06:42:26 +01:00
Honza
9aa0fb1858 Added broken array multiplier and truncated multiplier implementations. Tried testing them, but seems buggy. Needs further work. 2022-01-06 06:39:58 +01:00
Honza
f830029c54 Added truncated multiplier circuit implementation. Needs testing. 2022-01-04 03:13:21 +01:00
Honza
c8ed08691f Updated functionality of the extend_bus method. 2021-11-16 00:02:52 +01:00
Honza
2083ed35a1 Returned inner circuit's input buses extension feature back to its original form. 2021-11-15 22:58:34 +01:00
honzastor
f582ee729e Updated generation of hierarchical circuits to allow proper naming consistency between the subcomponent modules and their corresponding invocations. 2021-10-25 01:11:34 +02:00
honzastor
5d41997560 Added assertion checks for the same input bus lengths when initializing arithmetic circuits. 2021-10-24 18:48:00 +02:00
Vojta Mrazek
49cf3150ca
Merge pull request #7 from ehw-fit/devel 
Signed version
 2021-10-11 08:02:52 +02:00
honzastor
d41c5f3c94 Updated exportation of signed arithmetic circuits to python representation. Also unified some methods from arithmetic_circuit.py into general_circuit.py. 2021-10-10 22:15:13 +02:00
honzastor
cfb5bba3ec Bitwise and operation fix. 2021-10-10 00:02:58 +02:00
honzastor
16c1757bc3 Added signedness support for the output C code representation. Also modified the testing scripts and the chr2c.py converter accordingly and did some documentation changes (even made a small change in readme.md). Signedness support for the output python representation is TBD. 2021-10-09 23:45:54 +02:00
Vojta Mrazek
598c10e052 Merge branch 'main' of github.com:ehw-fit/ariths-gen 2021-10-04 12:19:55 +02:00
Vojta Mrazek
152a6b1583
Python eval (#4) 
* #3 basic clean up arithmetic circuit and general circuit

* #3 implementation of python generator

* #3 pytest in actions

* #3 pytest in actions fix
 2021-10-04 11:58:28 +02:00
Vojta Mrazek
995107eecc Removing of file closing 2021-09-23 08:50:18 +02:00
Vojta Mrazek
bee2086705
Devel (#2) 
* CGP format

* CGP format minor

* General MAC circuit

* Modified definition of MAC class to allow proper generation of output representations.

* auto test MAC

* test all

* Made some minor changes and updated creation of MAC circuit.

* Updated logic behind generating export representations, mainly focused around circuit and its buses and subcomponents namings.

* Made some minor changes concerning proper exportation of multiplier circuits.

Co-authored-by: honzastor <jan.klhufek@gmail.com>
 2021-09-18 12:55:31 +02:00
honzastor
eba0a7a938 Made some minor changes concerning proper exportation of multiplier circuits. 2021-09-09 13:57:36 +02:00
honzastor
e16de78c2b Updated logic behind generating export representations, mainly focused around circuit and its buses and subcomponents namings. 2021-09-07 17:39:39 +02:00