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Update setup.cfg
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[metadata]
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name = ariths_gen
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description = Arithmetic circuits generator to Verilog, BLIF, C etc.
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version = attr: ariths_gen.VERSION
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long_description = file: README.md
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long_description_content_type = text/markdown
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license = MIT
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author = Jan Klhufek, Vojtech Mrazek
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author_email = iklhufek@fit.vutbr.cz
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@ -17,3 +16,4 @@ project_urls =
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[options]
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packages = find:
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python_requires = >=3.8
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