Update setup.cfg
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Vojta Mrazek 2024-12-13 12:51:46 +01:00 committed by GitHub
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@ -1,10 +1,9 @@
[metadata]
name = ariths_gen
description = Arithmetic circuits generator to Verilog, BLIF, C etc.
version = attr: ariths_gen.VERSION
long_description = file: README.md
long_description_content_type = text/markdown
license = MIT
author = Jan Klhufek, Vojtech Mrazek
author_email = iklhufek@fit.vutbr.cz
@ -17,3 +16,4 @@ project_urls =
[options]
packages = find:
python_requires = >=3.8