Lukas Plevac
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09a12f3df7
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Fully working xorGateComponent
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2024-10-10 13:33:09 +02:00 |
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Lukas Plevac
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ad9f62e3de
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Added support for MIG excluded xor and xnor gate
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2024-10-07 15:19:55 +02:00 |
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Vojta
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c1e8680e83
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CGP with more than 26 inputs naming
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2024-10-03 08:18:49 +02:00 |
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Vojta Mrazek
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04cd3e44d3
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bug in cgp indexes with constant wires, they were encouted
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2024-07-22 15:09:50 +02:00 |
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Vojta Mrazek
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f34471bfe3
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signed version of python code
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2024-07-18 13:16:15 +02:00 |
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Vojta Mrazek
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4cd1189d4a
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CGP circuit accepts BUS inputs
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2024-07-18 13:15:56 +02:00 |
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Vojta Mrazek
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bc0104de12
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ripple cary subtractor
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2024-07-09 09:22:11 +02:00 |
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honzastor
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ce36ebf77b
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Fixed hierarchical BLIF generation for popcount_compare.
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2024-04-17 18:47:41 +02:00 |
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honzastor
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6003886eb7
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Fixed hierarchical Verilog generation of popcount compare. BLIF probably needs a similar treatment, TBD later
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2024-04-14 16:29:10 +02:00 |
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honzastor
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97e79b93da
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Big code cleanup and some fixes. Hierarchical generation for popcount seems problematic. It seems bus connections are the issue.
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2024-04-13 17:04:03 +02:00 |
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honzastor
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739d5fafce
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Added documentation to Recursive multiplier and hopefully fixed some issues with popcount output generation.
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2024-04-08 21:37:34 +02:00 |
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Vojta Mrazek
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1219d7bec5
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Merge branch 'popcount' into devel
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2024-04-05 09:19:04 +02:00 |
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Vojta Mrazek
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2cf7b921ea
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Popcount implementation
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2024-04-05 08:46:02 +02:00 |
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honzastor
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da733cf44e
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Added instantiation of wires and buses from inputs. Hopefully fixed now.
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2024-03-28 00:06:53 +01:00 |
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honzastor
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d013a40145
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Added unsigned recursive multiplier and made some bugfixes.
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2024-03-27 23:00:13 +01:00 |
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Vojta Mrazek
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2e1694ccd5
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popcount and compare
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2024-03-22 14:19:23 +01:00 |
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honzastor
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7e1112cf81
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Added individual input bus attributes to CGP Circuit objects to allow for the generation of output CGP representation.
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2024-03-06 00:42:12 +01:00 |
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Vojta Mrazek
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f853a46703
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CGP circuit checks
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2023-04-13 12:09:07 +02:00 |
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honzastor
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7cf34d04f3
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Bugfix in conditional statement.
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2023-03-22 18:14:55 +01:00 |
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honzastor
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b88c502343
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Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated).
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2023-03-22 17:57:51 +01:00 |
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honzastor
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d52e67bb25
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Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.
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2023-02-24 11:13:46 +01:00 |
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Vojta Mrazek
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71a1d45045
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string description (#15)
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2023-02-22 09:45:14 +01:00 |
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Honza
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c0dcf42499
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Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.
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2022-04-17 13:04:17 +02:00 |
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Honza
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9e186d10ed
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Typos fix and code cleanup.
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2022-02-18 17:24:09 +01:00 |
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Honza
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6f05db002e
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Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup.
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2022-02-18 17:00:31 +01:00 |
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Vojta Mrazek
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3c47407f80
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output rename
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2022-02-07 11:29:12 +01:00 |
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Vojta Mrazek
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1e44c2e3dc
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#10 CGP Circuits as inputs (#11)
* CGP Circuits as inputs
* #10 support of signed output in general circuit
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2022-02-01 13:23:26 +01:00 |
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Honza
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d9b56e8a00
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Fixed generation of unsigned variants of BAM and TM multipliers. Signed versions don't guarantee correct funcionality atm.
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2022-01-06 19:23:56 +01:00 |
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Honza
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9aa0fb1858
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Added broken array multiplier and truncated multiplier implementations. Tried testing them, but seems buggy. Needs further work.
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2022-01-06 06:39:58 +01:00 |
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Honza
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f830029c54
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Added truncated multiplier circuit implementation. Needs testing.
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2022-01-04 03:13:21 +01:00 |
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honzastor
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f582ee729e
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Updated generation of hierarchical circuits to allow proper naming consistency between the subcomponent modules and their corresponding invocations.
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2021-10-25 01:11:34 +02:00 |
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honzastor
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5d41997560
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Added assertion checks for the same input bus lengths when initializing arithmetic circuits.
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2021-10-24 18:48:00 +02:00 |
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honzastor
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d41c5f3c94
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Updated exportation of signed arithmetic circuits to python representation. Also unified some methods from arithmetic_circuit.py into general_circuit.py.
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2021-10-10 22:15:13 +02:00 |
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honzastor
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cfb5bba3ec
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Bitwise and operation fix.
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2021-10-10 00:02:58 +02:00 |
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honzastor
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16c1757bc3
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Added signedness support for the output C code representation. Also modified the testing scripts and the chr2c.py converter accordingly and did some documentation changes (even made a small change in readme.md). Signedness support for the output python representation is TBD.
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2021-10-09 23:45:54 +02:00 |
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Vojta Mrazek
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152a6b1583
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Python eval (#4)
* #3 basic clean up arithmetic circuit and general circuit
* #3 implementation of python generator
* #3 pytest in actions
* #3 pytest in actions fix
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2021-10-04 11:58:28 +02:00 |
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Vojta Mrazek
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995107eecc
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Removing of file closing
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2021-09-23 08:50:18 +02:00 |
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honzastor
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eba0a7a938
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Made some minor changes concerning proper exportation of multiplier circuits.
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2021-09-09 13:57:36 +02:00 |
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honzastor
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e16de78c2b
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Updated logic behind generating export representations, mainly focused around circuit and its buses and subcomponents namings.
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2021-09-07 17:39:39 +02:00 |
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Vojta Mrazek
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8c0f24cd2d
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General MAC circuit
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2021-09-06 12:52:13 +02:00 |
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Vojta Mrazek
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a4dca24fc2
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CGP format minor
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2021-06-23 14:09:46 +02:00 |
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Vojta Mrazek
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0a487ee699
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CGP format
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2021-06-23 14:08:49 +02:00 |
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Vojta Mrazek
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c6e542231c
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CGP tests; reversed output order
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2021-06-23 13:43:58 +02:00 |
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honzastor
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0f66c5a2e9
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Fixed proper connections in submodules instantiation in hierarchical Verilog generation. Sample generated circuits were also accordingly updated.
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2021-04-23 11:49:24 +02:00 |
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honzastor
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670ba45ee5
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Generated sample circuits for various representations. Updated C code circuits testing simulations and did some cleanup.
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2021-04-23 02:44:14 +02:00 |
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honzastor
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8e950fc51f
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Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits.
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2021-04-21 11:33:07 +02:00 |
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honzastor
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068def0226
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Added documentation of classes methods.
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2021-04-06 01:39:11 +02:00 |
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honzastor
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a336a683e7
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Added some code documentation and updated git action to generate it.
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2021-03-31 04:40:54 +02:00 |
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Jan Klhůfek
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87105eaaa6
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Delete ariths_gen/core/__pycache__ directory
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2021-03-30 03:11:13 +02:00 |
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honzastor
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69e2514852
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Updated project's structure. Renamed class names to properly fit Python naming convention. TBD: proper documentation.
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2021-03-30 03:04:48 +02:00 |
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