honzastor b88c502343 Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated).

2023-03-22 17:57:51 +01:00

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arithmetic_circuits

Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated).

2023-03-22 17:57:51 +01:00

logic_gate_circuits

Bitwise and operation fix.

2021-10-10 00:02:58 +02:00

one_bit_circuits

Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.

2023-02-24 11:13:46 +01:00

__init__.py

Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits.

2021-04-21 11:33:07 +02:00

cgp_circuit.py

Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.

2023-02-24 11:13:46 +01:00