This website requires JavaScript.
Explore
Help
Sign In
dissertation_thesis
/
ariths-gen-mig
Watch
1
Star
0
Fork
0
You've already forked ariths-gen-mig
Code
Issues
Pull Requests
Actions
Packages
Projects
Releases
Wiki
Activity
ariths-gen-mig
/
ariths_gen
/
core
History
honzastor
16c1757bc3
Added signedness support for the output C code representation. Also modified the testing scripts and the chr2c.py converter accordingly and did some documentation changes (even made a small change in readme.md). Signedness support for the output python representation is TBD.
2021-10-09 23:45:54 +02:00
..
arithmetic_circuits
Added signedness support for the output C code representation. Also modified the testing scripts and the chr2c.py converter accordingly and did some documentation changes (even made a small change in readme.md). Signedness support for the output python representation is TBD.
2021-10-09 23:45:54 +02:00
logic_gate_circuits
Added signedness support for the output C code representation. Also modified the testing scripts and the chr2c.py converter accordingly and did some documentation changes (even made a small change in readme.md). Signedness support for the output python representation is TBD.
2021-10-09 23:45:54 +02:00
one_bit_circuits
Added signedness support for the output C code representation. Also modified the testing scripts and the chr2c.py converter accordingly and did some documentation changes (even made a small change in readme.md). Signedness support for the output python representation is TBD.
2021-10-09 23:45:54 +02:00
__init__.py
Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits.
2021-04-21 11:33:07 +02:00