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ariths-gen-mig
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Static write FA to PGAdder
#28
:
Commit
e662c52e75
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lukasplevac
main
2025-01-19 18:12:34 +00:00
1m51s
Code generation fix
#27
:
Commit
6c8c791fb5
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main
2025-01-19 17:37:08 +00:00
1m58s
unexpected keyword argument 'parent_component'
#26
:
Commit
db25df54cd
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main
2025-01-15 18:35:02 +00:00
1m45s
Incorect FA instance create
#25
:
Commit
cf4a6ccc52
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lukasplevac
main
2025-01-15 18:31:32 +00:00
16s
Full adder missing import
#24
:
Commit
aefc20693a
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lukasplevac
main
2025-01-15 18:28:49 +00:00
17s
Imprt missing full adder
#23
:
Commit
395750eac5
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lukasplevac
main
2025-01-15 18:24:08 +00:00
17s
GCP PGA ADDER
#22
:
Commit
d0501238f8
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lukasplevac
main
2025-01-06 12:04:25 +00:00
27s
Update readme
#21
:
Commit
8adba05ba4
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main
2024-11-16 19:56:53 +00:00
1m45s
Simple generate example
#20
:
Commit
db231dd7f7
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2024-11-16 19:49:17 +00:00
1m48s
Aktualizovat README.md
#19
:
Commit
e576a9fd81
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lukasplevac
main
2024-11-14 14:49:58 +00:00
1m48s
Fix unsigned mul test
#18
:
Commit
bb94958118
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lukasplevac
main
2024-11-14 14:24:54 +00:00
1m51s
Remove iverilog from pipe
#17
:
Commit
5bb50a325f
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lukasplevac
main
2024-11-14 14:22:01 +00:00
1m35s
Fixing pipeline
#16
:
Commit
975ab01a1c
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lukasplevac
main
2024-11-14 14:19:26 +00:00
18s
Fix mux with wrong gate ordering
#15
:
Commit
c476479827
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lukasplevac
main
2024-11-14 14:19:06 +00:00
0s
All working muls and adders
#9
:
Commit
4eb65e10da
pushed by
lukasplevac
main
2024-10-19 14:32:36 +01:00
26m57s
Fully working xorGateComponent
#6
:
Commit
09a12f3df7
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lukasplevac
main
2024-10-11 15:40:01 +01:00
3s
Fixed RCA by test
#4
:
Commit
c61244c966
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lukasplevac
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2024-10-09 15:40:00 +01:00
2s
Added support for MIG excluded xor and xnor gate
#2
:
Commit
ad9f62e3de
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lukasplevac
main
2024-10-08 13:29:08 +01:00
3s