honzastor
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792d0c5db1
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Did some code refactoring concerning one bit circuits generation. Added multiple one/multi bit circuits. TBD: Generate and test different circuits, implement divider circuits, comment code, add verification/optimization of Verilog/BLIF files using yosys tool.
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2021-03-22 00:22:01 +01:00 |
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honzastor
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d86ddcac09
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Implemented unsigned dadda multiplier circuit. Updated generation of export formats. TBD: Proper testing, modification of dadda with cla adder, write shell script for Verilog and Blif equivalence check.
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2021-03-15 01:08:47 +01:00 |
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honzastor
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f76284fcaa
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Updated cgp chromosomes for 1 bit multipliers.
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2021-03-04 19:34:08 +01:00 |
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honzastor
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f28069da5f
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Refactored code and made some small bugfixes for generating exports.
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2021-03-04 18:57:32 +01:00 |
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honzastor
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e4722c662d
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Implemented multiplier circuits, verilog and cgp export generation and changed generator's structure. Prone to error! Needs proper testing. TBD
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2021-03-01 21:32:29 +01:00 |
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honzastor
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ef5dc80382
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Implemented generation to flat Verilog format and improved some other minor bits of code.
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2021-02-16 10:41:29 +01:00 |
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honzastor
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397d3bc658
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Added generation of hierarchical C code for implemented circuits.
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2021-02-12 01:43:44 +01:00 |
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honzastor
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de127e8c46
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Added signed rca circuit.
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2021-02-09 20:53:53 +01:00 |
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honzastor
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ee73047199
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Edited example circuits generation.
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2021-01-18 19:34:05 +01:00 |
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honzastor
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4f8de30911
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Implementation organized into multiple scripts. Added basic generation example call. Adjusting code to PEP8 standard (except long lines).)
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2021-01-18 19:29:31 +01:00 |
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root
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b7c896872e
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Made small bugfixes in C code generation.
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2020-12-28 15:11:22 +01:00 |
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root
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6fe6d2c3d6
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Changed implementaion of generating C code from circuits.
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2020-12-28 01:30:52 +01:00 |
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root
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67a1dfa148
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Updated C code generation wire names.
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2020-12-13 14:53:20 +01:00 |
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root
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01f473e727
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Added c code generation for logic gates, one bit adders, rca.
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2020-12-11 22:57:32 +01:00 |
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root
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f18f6159f5
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Started work on exporting adders into .c files. Needs optimization.
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2020-12-11 03:48:04 +01:00 |
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root
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7fba0f0aea
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Added ripple carry adder and started work on C code generation.
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2020-12-10 22:37:10 +01:00 |
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root
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99d23be531
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Implemented logic for wire, bus, logic gates, and 1-bit adders.
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2020-12-10 03:52:00 +01:00 |
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