Vojta Mrazek
bc95444995
reconnected wire was not identified as a bus
2024-07-22 15:10:21 +02:00
Vojta Mrazek
f34471bfe3
signed version of python code
2024-07-18 13:16:15 +02:00
honzastor
ce36ebf77b
Fixed hierarchical BLIF generation for popcount_compare.
2024-04-17 18:47:41 +02:00
honzastor
6003886eb7
Fixed hierarchical Verilog generation of popcount compare. BLIF probably needs a similar treatment, TBD later
2024-04-14 16:29:10 +02:00
honzastor
97e79b93da
Big code cleanup and some fixes. Hierarchical generation for popcount seems problematic. It seems bus connections are the issue.
2024-04-13 17:04:03 +02:00
Vojta Mrazek
1219d7bec5
Merge branch 'popcount' into devel
2024-04-05 09:19:04 +02:00
Vojta Mrazek
2cf7b921ea
Popcount implementation
2024-04-05 08:46:02 +02:00
honzastor
d013a40145
Added unsigned recursive multiplier and made some bugfixes.
2024-03-27 23:00:13 +01:00
Vojta Mrazek
2e1694ccd5
popcount and compare
2024-03-22 14:19:23 +01:00
Vojta Mrazek
f853a46703
CGP circuit checks
2023-04-13 12:09:07 +02:00
Vojta Mrazek
a4741db191
connection checks (asserts)
2023-03-28 11:16:55 +02:00
Vojta Mrazek
49bbc86a0f
accepts a wire as a bus
2023-03-23 13:39:32 +01:00
honzastor
d52e67bb25
Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.
2023-02-24 11:13:46 +01:00
Vojta Mrazek
283f9c79f5
Merge branch 'main' into devel
2023-02-22 12:12:20 +01:00
Vojta Mrazek
6dd69c5aaa
Merge branch 'devel' of github.com:ehw-fit/ariths-gen into devel
2023-02-22 09:52:34 +01:00
Vojta Mrazek
43b3d65463
workflow modification, bus indexing
2023-02-22 09:52:06 +01:00
Vojta Mrazek
71a1d45045
string description ( #15 )
2023-02-22 09:45:14 +01:00
Vojta Mrazek
35240abc63
fix bug in python interpretation
2023-02-22 09:43:24 +01:00
Jan Klhůfek
56c86c13ca
New multipliers ( #13 )
...
* #10 CGP Circuits as inputs (#11 )
* CGP Circuits as inputs
* #10 support of signed output in general circuit
* input as output works
* output connected to input (c)
* automated verilog testing
* output rename
* Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup.
* Typos fix and code cleanup.
* Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.
* Updated automated testing scripts.
* Small bugfix in python code generation (I initially thought this line is useless).
* Updated generated circuits folder.
Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
2022-04-17 16:00:00 +02:00
Honza
b1ddc8c387
Small bugfix in python code generation (I initially thought this line is useless).
2022-04-17 13:25:10 +02:00
Honza
c0dcf42499
Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.
2022-04-17 13:04:17 +02:00
Honza
6f05db002e
Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup.
2022-02-18 17:00:31 +01:00
Vojta Mrazek
ee8621ef4d
output connected to input (c)
2022-02-02 12:53:18 +01:00
Vojta Mrazek
dc705106b4
input as output works
2022-02-02 11:19:32 +01:00
Honza
c8ed08691f
Updated functionality of the extend_bus method.
2021-11-16 00:02:52 +01:00
honzastor
5d41997560
Added assertion checks for the same input bus lengths when initializing arithmetic circuits.
2021-10-24 18:48:00 +02:00
honzastor
d41c5f3c94
Updated exportation of signed arithmetic circuits to python representation. Also unified some methods from arithmetic_circuit.py into general_circuit.py.
2021-10-10 22:15:13 +02:00
honzastor
cfb5bba3ec
Bitwise and operation fix.
2021-10-10 00:02:58 +02:00
honzastor
16c1757bc3
Added signedness support for the output C code representation. Also modified the testing scripts and the chr2c.py converter accordingly and did some documentation changes (even made a small change in readme.md). Signedness support for the output python representation is TBD.
2021-10-09 23:45:54 +02:00
Vojta Mrazek
152a6b1583
Python eval ( #4 )
...
* #3 basic clean up arithmetic circuit and general circuit
* #3 implementation of python generator
* #3 pytest in actions
* #3 pytest in actions fix
2021-10-04 11:58:28 +02:00
honzastor
e16de78c2b
Updated logic behind generating export representations, mainly focused around circuit and its buses and subcomponents namings.
2021-09-07 17:39:39 +02:00
honzastor
0f66c5a2e9
Fixed proper connections in submodules instantiation in hierarchical Verilog generation. Sample generated circuits were also accordingly updated.
2021-04-23 11:49:24 +02:00
honzastor
670ba45ee5
Generated sample circuits for various representations. Updated C code circuits testing simulations and did some cleanup.
2021-04-23 02:44:14 +02:00
honzastor
8e950fc51f
Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits.
2021-04-21 11:33:07 +02:00
honzastor
a336a683e7
Added some code documentation and updated git action to generate it.
2021-03-31 04:40:54 +02:00
Jan Klhůfek
669920b0d5
Delete ariths_gen/wire_components/__pycache__ directory
2021-03-30 03:12:11 +02:00
honzastor
69e2514852
Updated project's structure. Renamed class names to properly fit Python naming convention. TBD: proper documentation.
2021-03-30 03:04:48 +02:00
