honzastor 6003886eb7 Fixed hierarchical Verilog generation of popcount compare. BLIF probably needs a similar treatment, TBD later

2024-04-14 16:29:10 +02:00

..

__init__.py

Generated sample circuits for various representations. Updated C code circuits testing simulations and did some cleanup.

2021-04-23 02:44:14 +02:00

buses.py

Fixed hierarchical Verilog generation of popcount compare. BLIF probably needs a similar treatment, TBD later

2024-04-14 16:29:10 +02:00

wires.py

Fixed hierarchical Verilog generation of popcount compare. BLIF probably needs a similar treatment, TBD later

2024-04-14 16:29:10 +02:00