Vojta Mrazek
1c2efef024
automated verilog testing
2022-02-02 13:19:54 +01:00
Vojta Mrazek
ee8621ef4d
output connected to input (c)
2022-02-02 12:53:18 +01:00
Vojta Mrazek
dc705106b4
input as output works
2022-02-02 11:19:32 +01:00
Vojta Mrazek
1e44c2e3dc
#10 CGP Circuits as inputs ( #11 )
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* CGP Circuits as inputs
* #10 support of signed output in general circuit
2022-02-01 13:23:26 +01:00
Vojta Mrazek
5646334b7f
workflow axmult typo
2022-01-13 16:11:48 +01:00
Vojta Mrazek
aeacd72d24
Readme, axmults in workflow
2022-01-13 16:10:51 +01:00
Honza
13c085f169
Fixed a small bug – missing ending semicolon in generation of library desired HA/FA to Verilog. Added script for generation of AX multipliers.
2022-01-13 13:11:24 +01:00
Vojta Mrazek
d641595c3e
Support of PDK in HA and FA
2022-01-13 12:37:09 +01:00
Honza
18b44226d8
Small bugfixes and removal of redundant code.
2022-01-07 20:36:51 +01:00
Honza
d9b56e8a00
Fixed generation of unsigned variants of BAM and TM multipliers. Signed versions don't guarantee correct funcionality atm.
2022-01-06 19:23:56 +01:00
Honza
2075c0edf5
Another fix
2022-01-06 06:46:11 +01:00
Honza
b66c1bdfe0
Import fix
2022-01-06 06:42:26 +01:00
Honza
9aa0fb1858
Added broken array multiplier and truncated multiplier implementations. Tried testing them, but seems buggy. Needs further work.
2022-01-06 06:39:58 +01:00
Honza
f830029c54
Added truncated multiplier circuit implementation. Needs testing.
2022-01-04 03:13:21 +01:00
Honza
c8ed08691f
Updated functionality of the extend_bus method.
2021-11-16 00:02:52 +01:00
Honza
2083ed35a1
Returned inner circuit's input buses extension feature back to its original form.
2021-11-15 22:58:34 +01:00
honzastor
f582ee729e
Updated generation of hierarchical circuits to allow proper naming consistency between the subcomponent modules and their corresponding invocations.
2021-10-25 01:11:34 +02:00
honzastor
5d41997560
Added assertion checks for the same input bus lengths when initializing arithmetic circuits.
2021-10-24 18:48:00 +02:00
Vojta Mrazek
49cf3150ca
Merge pull request #7 from ehw-fit/devel
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Signed version
2021-10-11 08:02:52 +02:00
honzastor
d41c5f3c94
Updated exportation of signed arithmetic circuits to python representation. Also unified some methods from arithmetic_circuit.py into general_circuit.py.
2021-10-10 22:15:13 +02:00
honzastor
cfb5bba3ec
Bitwise and operation fix.
2021-10-10 00:02:58 +02:00
honzastor
16c1757bc3
Added signedness support for the output C code representation. Also modified the testing scripts and the chr2c.py converter accordingly and did some documentation changes (even made a small change in readme.md). Signedness support for the output python representation is TBD.
2021-10-09 23:45:54 +02:00
Vojta Mrazek
598c10e052
Merge branch 'main' of github.com:ehw-fit/ariths-gen
2021-10-04 12:19:55 +02:00
Vojta Mrazek
152a6b1583
Python eval ( #4 )
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* #3 basic clean up arithmetic circuit and general circuit
* #3 implementation of python generator
* #3 pytest in actions
* #3 pytest in actions fix
2021-10-04 11:58:28 +02:00
Vojta Mrazek
995107eecc
Removing of file closing
2021-09-23 08:50:18 +02:00
Vojta Mrazek
bee2086705
Devel ( #2 )
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* CGP format
* CGP format minor
* General MAC circuit
* Modified definition of MAC class to allow proper generation of output representations.
* auto test MAC
* test all
* Made some minor changes and updated creation of MAC circuit.
* Updated logic behind generating export representations, mainly focused around circuit and its buses and subcomponents namings.
* Made some minor changes concerning proper exportation of multiplier circuits.
Co-authored-by: honzastor <jan.klhufek@gmail.com>
2021-09-18 12:55:31 +02:00
honzastor
eba0a7a938
Made some minor changes concerning proper exportation of multiplier circuits.
2021-09-09 13:57:36 +02:00
honzastor
e16de78c2b
Updated logic behind generating export representations, mainly focused around circuit and its buses and subcomponents namings.
2021-09-07 17:39:39 +02:00
honzastor
bfc806081e
Made some minor changes and updated creation of MAC circuit.
2021-09-07 17:35:41 +02:00
Vojta Mrazek
f1303864ca
test all
2021-09-07 09:44:23 +02:00
Vojta Mrazek
fffb928875
auto test MAC
2021-09-07 08:32:52 +02:00
honzastor
a1827c957c
Modified definition of MAC class to allow proper generation of output representations.
2021-09-06 15:17:31 +02:00
Vojta Mrazek
8c0f24cd2d
General MAC circuit
2021-09-06 12:52:13 +02:00
Vojta Mrazek
a4dca24fc2
CGP format minor
2021-06-23 14:09:46 +02:00
Vojta Mrazek
0a487ee699
CGP format
2021-06-23 14:08:49 +02:00
Vojta Mrazek
87a7f2b8bb
pip in actions
2021-06-23 13:46:25 +02:00
Vojta Mrazek
c6e542231c
CGP tests; reversed output order
2021-06-23 13:43:58 +02:00
Vojta Mrazek
5228923b69
doc on main branch only
2021-06-18 12:40:56 +02:00
Vojta Mrazek
cfe0ca6b4b
Automated testing, preparing the package for publishing ( #1 )
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* automated pandoc deploy
* automated pandoc deploy (v2)
* automated pandoc deploy (v2)
* automated pdoc deploy (v3)
* automated pdoc deploy (v4)
* automated pdoc deploy (v5)
* automated pdoc deploy (v5)
* prepare for python project
* 8-bit testing
* 8-bit testing
* 8-bit testing (v2)
* 8-bit testing (v3)
* update of sign
2021-06-18 12:38:11 +02:00
honzastor
f1f487a126
Small fix
2021-05-05 18:30:21 +02:00
honzastor
0d98fc0a2f
Adding generated program documentation and chr2c.py script.
2021-05-05 18:27:47 +02:00
honzastor
50c33d27d2
Updated generated circuits.
2021-04-28 21:47:33 +02:00
honzastor
e5f2dd893a
Fixed proper generated circuits names (mistakenly named cska as csa).
2021-04-28 21:39:58 +02:00
Jan Klhůfek
f6838e50bd
Merge pull request #4 from honzastor/develop
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Merging current final state of ArithsGen into main branch.
2021-04-24 00:04:31 +02:00
honzastor
4740371c06
Deleted presentation of previous generator state.
2021-04-24 00:00:48 +02:00
honzastor
0f66c5a2e9
Fixed proper connections in submodules instantiation in hierarchical Verilog generation. Sample generated circuits were also accordingly updated.
2021-04-23 11:49:24 +02:00
honzastor
a17e38b2d1
Uploading C code circuit simulations.
2021-04-23 02:48:32 +02:00
honzastor
670ba45ee5
Generated sample circuits for various representations. Updated C code circuits testing simulations and did some cleanup.
2021-04-23 02:44:14 +02:00
honzastor
f57a633f6c
Renamed generated circuits folders.
2021-04-22 20:56:38 +02:00
honzastor
8f911560b0
Folder renaming test
2021-04-22 20:23:57 +02:00
