Added assertion checks for the same input bus lengths when initializing arithmetic circuits.

ariths_gen/core/arithmetic_circuits/multiplier_circuit.py

@@ -29,7 +29,7 @@ class MultiplierCircuit(ArithmeticCircuit):
     that are later used for generation into various representations.
     """
 
-    def __init__(self, a, b, prefix, name, out_N, **kwargs):
+    def __init__(self, a, b, prefix: str, name: str, out_N: int, **kwargs):
         super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=out_N, **kwargs)
 
     # Array multipliers

ariths_gen/multi_bit_circuits/adders/carry_lookahead_adder.py

@@ -66,12 +66,9 @@ class UnsignedCarryLookaheadAdder(ArithmeticCircuit):
         name (str, optional): Name of unsigned cla. Defaults to "u_cla".
     """
     def __init__(self, a: Bus, b: Bus, cla_block_size: int = 4, prefix: str = "", name: str = "u_cla", **kwargs):
+        assert a.N == b.N
         self.N = max(a.N, b.N)
-        super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N+1, **kwargs)        
-
-        # Bus sign extension in case buses have different lengths
-        self.a.bus_extend(N=self.N, prefix=a.prefix)
-        self.b.bus_extend(N=self.N, prefix=b.prefix)
+        super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N+1, **kwargs)
 
         # To signify current number of blocks and number of bits that remain to be added into function blocks
         N_blocks = 0

ariths_gen/multi_bit_circuits/adders/carry_skip_adder.py

@@ -73,13 +73,10 @@ class UnsignedCarrySkipAdder(ArithmeticCircuit):
         name (str, optional): Name of unsigned cska. Defaults to "u_cska".
     """
     def __init__(self, a: Bus, b: Bus, bypass_block_size: int = 4, prefix: str = "", name: str = "u_cska", **kwargs):
+        assert a.N == b.N
         self.N = max(a.N, b.N)
         super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N+1, **kwargs)
 
-        # Bus sign extension in case buses have different lengths
-        self.a.bus_extend(N=self.N, prefix=a.prefix)
-        self.b.bus_extend(N=self.N, prefix=b.prefix)
-
         # To signify current number of blocks and number of bits that remain to be added into function blocks
         N_blocks = 0
         N_wires = self.N

ariths_gen/multi_bit_circuits/adders/pg_ripple_carry_adder.py

@@ -63,12 +63,9 @@ class UnsignedPGRippleCarryAdder(ArithmeticCircuit):
         name (str, optional): Name of unsigned P/G rca. Defaults to "u_pg_rca".
     """
     def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "u_pg_rca", **kwargs):
+        assert a.N == b.N
         self.N = max(a.N, b.N)
         super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N+1, **kwargs)
-        
-        # Bus sign extension in case buses have different lengths
-        self.a.bus_extend(N=self.N, prefix=a.prefix)
-        self.b.bus_extend(N=self.N, prefix=b.prefix)
 
         # Gradual addition of 1-bit adder components
         for input_index in range(self.N):

ariths_gen/multi_bit_circuits/adders/ripple_carry_adder.py

@@ -54,13 +54,10 @@ class UnsignedRippleCarryAdder(ArithmeticCircuit):
         name (str, optional): Name of unsigned rca. Defaults to "u_rca".
     """
     def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "u_rca", **kwargs):
+        assert a.N == b.N
         self.N = max(a.N, b.N)
         super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N+1, **kwargs)
 
-        # Bus sign extension in case buses have different lengths
-        self.a.bus_extend(N=self.N, prefix=a.prefix)
-        self.b.bus_extend(N=self.N, prefix=b.prefix)
-
         # Gradual addition of 1-bit adder components
         for input_index in range(self.N):
             # First adder is a half adder

ariths_gen/multi_bit_circuits/dividers/array_divider.py

@@ -96,13 +96,10 @@ class ArrayDivider(ArithmeticCircuit):
         name (str, optional): Name of array divider. Defaults to "arrdiv".
     """
     def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "arrdiv", **kwargs):
+        assert a.N == b.N
         self.N = max(a.N, b.N)
         super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N, **kwargs)
 
-        # Bus sign extension in case buses have different lengths
-        self.a.bus_extend(N=self.N, prefix=a.prefix)
-        self.b.bus_extend(N=self.N, prefix=b.prefix)
-
         # Performing series of iterative subtractions
         # Gradually shifting the divisor
         for a_index in reversed(range(self.N)):

ariths_gen/multi_bit_circuits/multipliers/array_multiplier.py

@@ -83,13 +83,10 @@ class UnsignedArrayMultiplier(MultiplierCircuit):
         name (str, optional): Name of unsigned array multiplier. Defaults to "u_arrmul".
     """
     def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "u_arrmul", **kwargs):
+        assert a.N == b.N
         self.N = max(a.N, b.N)
         super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, **kwargs)
 
-        # Bus sign extension in case buses have different lengths
-        self.a.bus_extend(N=self.N, prefix=a.prefix)
-        self.b.bus_extend(N=self.N, prefix=b.prefix)
-
         # Gradual generation of partial products
         for b_multiplier_index in range(self.N):
             for a_multiplicand_index in range(self.N):
@@ -190,14 +187,11 @@ class SignedArrayMultiplier(MultiplierCircuit):
         name (str, optional): Name of signed array multiplier. Defaults to "s_arrmul".
     """
     def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "s_arrmul", **kwargs):
+        assert a.N == b.N
         self.N = max(a.N, b.N)
         super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, signed=True, **kwargs)
         self.c_data_type = "int64_t"
 
-        # Bus sign extension in case buses have different lengths
-        self.a.bus_extend(N=self.N, prefix=a.prefix)
-        self.b.bus_extend(N=self.N, prefix=b.prefix)
-
         # Gradual generation of partial products
         for b_multiplier_index in range(self.N):
             for a_multiplicand_index in range(self.N):

ariths_gen/multi_bit_circuits/multipliers/dadda_multiplier.py

@@ -50,13 +50,10 @@ class UnsignedDaddaMultiplier(MultiplierCircuit):
         unsigned_adder_class_name (str, optional): Unsigned multi bit adder used to obtain final sums of products. Defaults to UnsignedCarryLookaheadAdder.
     """
     def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "u_dadda_cla", unsigned_adder_class_name: str = UnsignedCarryLookaheadAdder, **kwargs):
+        assert a.N == b.N
         self.N = max(a.N, b.N)
         super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, **kwargs)
 
-        # Bus sign extension in case buses have different lengths
-        self.a.bus_extend(N=self.N, prefix=a.prefix)
-        self.b.bus_extend(N=self.N, prefix=b.prefix)
-
         # Get starting stage and maximum possible column height
         self.stage, self.d = self.get_maximum_height(initial_value=min(self.a.N, self.b.N))
         # Initialize all columns partial products forming AND gates matrix
@@ -154,14 +151,11 @@ class SignedDaddaMultiplier(MultiplierCircuit):
         unsigned_adder_class_name (str, optional): Unsigned multi bit adder used to obtain final sums of products. Defaults to UnsignedCarryLookaheadAdder.
     """
     def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "s_dadda_cla", unsigned_adder_class_name: str = UnsignedCarryLookaheadAdder, **kwargs):
+        assert a.N == b.N
         self.N = max(a.N, b.N)
         super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, signed=True, **kwargs)
         self.c_data_type = "int64_t"
 
-        # Bus sign extension in case buses have different lengths
-        self.a.bus_extend(N=self.N, prefix=a.prefix)
-        self.b.bus_extend(N=self.N, prefix=b.prefix)
-
         # Get starting stage and maximum possible column height
         self.stage, self.d = self.get_maximum_height(initial_value=min(self.a.N, self.b.N))
         # Initialize all columns partial products forming AND/NAND gates matrix based on Baugh-Wooley multiplication

ariths_gen/multi_bit_circuits/multipliers/wallace_multiplier.py

@@ -49,13 +49,10 @@ class UnsignedWallaceMultiplier(MultiplierCircuit):
         unsigned_adder_class_name (str, optional): Unsigned multi bit adder used to obtain final sums of products. Defaults to UnsignedCarryLookaheadAdder.
     """
     def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "u_wallace_cla", unsigned_adder_class_name: str = UnsignedCarryLookaheadAdder, **kwargs):
+        assert a.N == b.N
         self.N = max(a.N, b.N)
         super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, **kwargs)
 
-        # Bus sign extension in case buses have different lengths
-        self.a.bus_extend(N=self.N, prefix=a.prefix)
-        self.b.bus_extend(N=self.N, prefix=b.prefix)
-
         # Initialize all columns partial products forming AND gates matrix
         self.columns = self.init_column_heights()
 
@@ -147,14 +144,11 @@ class SignedWallaceMultiplier(MultiplierCircuit):
         unsigned_adder_class_name (str, optional): Unsigned multi bit adder used to obtain final sums of products. Defaults to UnsignedCarryLookaheadAdder.
     """
     def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "s_wallace_cla", unsigned_adder_class_name: str = UnsignedCarryLookaheadAdder, **kwargs):
+        assert a.N == b.N
         self.N = max(a.N, b.N)
         super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, signed=True, **kwargs)
         self.c_data_type = "int64_t"
 
-        # Bus sign extension in case buses have different lengths
-        self.a.bus_extend(N=self.N, prefix=a.prefix)
-        self.b.bus_extend(N=self.N, prefix=b.prefix)
-
         # Initialize all columns partial products forming AND/NAND gates matrix based on Baugh-Wooley multiplication
         self.columns = self.init_column_heights(signed=True)
 

ariths_gen/wire_components/buses.py

@@ -9,7 +9,7 @@ class Bus():
     Args:
         prefix (str, optional): Prefix name of the bus. Defaults to "bus".
         N (int, optional): Number of wires in the bus. Defaults to 1.
-        wires_list (list, optional): List of Wire objects used to clone one bus to another. Defaults to 0.
+        wires_list (list, optional): List of Wire objects used to clone one bus to another. Defaults to None.
         out_bus (bool, optional): Specifies whether this Bus is an output bus of some previous component. Defaults to False.
         signed (bool, optional): Specifies whether this Bus should consider signed numbers or not (used for C code generation). Defaults to False.
     """