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https://github.com/ehw-fit/ariths-gen.git
synced 2025-04-10 09:12:11 +01:00
Made some minor changes and updated creation of MAC circuit.
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honzastor
parent
f1303864ca
commit
bfc806081e
@ -1,5 +1,5 @@
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python generate_test.sh
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python generate_mac.sh
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python generate_test.py
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python generate_mac.py
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cd tests
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bash test_mac.sh
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bash test_circuits.sh
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@ -1,4 +1,5 @@
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from ariths_gen.core.arithmetic_circuits.arithmetic_circuit import ArithmeticCircuit
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from ariths_gen.core.arithmetic_circuits import GeneralCircuit
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from ariths_gen.wire_components import Bus, Wire
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from ariths_gen.multi_bit_circuits.adders import UnsignedRippleCarryAdder
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@ -6,55 +7,22 @@ from ariths_gen.multi_bit_circuits.multipliers import UnsignedArrayMultiplier
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import os
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class MAC(GeneralCircuit):
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def __init__(self, A:Bus, B:Bus, R:Bus):
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self.prefix = "mac"
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super().__init__([A, B, R])
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def __init__(self, A:Bus, B:Bus, R:Bus, prefix= "mac", **kwargs):
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super().__init__(prefix=prefix, out_N=2*A.N+1, inputs=[A, B, R], **kwargs)
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assert A.N == B.N
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assert R.N == 2 * A.N
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self.mul = self.add_component(UnsignedArrayMultiplier(a=A, b=B, prefix=self.prefix, inner_component=True))
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self.add = self.add_component(UnsignedRippleCarryAdder(a=R, b=self.mul.out, prefix=self.prefix, inner_component=True))
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self.out.connect_bus(connecting_bus=self.add.out)
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if False:
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# Je zapotřebí zajistit ještě unikátnost jmen podkomponent a jejich vodičů pro správné generování
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mul_a = Bus(prefix=f"{self.prefix}_mul_a", wires_list=A.bus)
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mul_b = Bus(prefix=f"{self.prefix}_mul_b", wires_list=B.bus)
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self.mul = self.add_component(UnsignedArrayMultiplier(a=mul_a, b=mul_b, prefix=f"{self.prefix}_mul"))
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add_a = Bus(prefix=f"{self.prefix}_add_a", N=self.mul.out.N)
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add_b = Bus(prefix=f"{self.prefix}_add_b", wires_list=R.bus)
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# Kvůli správnému generování je potřeba správně napojit vodiče mezi mul a add
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[add_a.connect(o, self.mul.out.get_wire(o), inserted_wire_desired_index=o) for o in range(0, self.mul.out.N)]
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self.add = self.add_component(UnsignedRippleCarryAdder(a=add_a, b=add_b, prefix=f"{self.prefix}_add"))
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# Bylo potřeba upravit definici pro výstupní sběrnici (vázanou na název top level obvodu ("ma") a mající délku jako výstup z adderu)
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self.out = Bus(self.prefix+"_out", self.add.out.N)
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# Nakonec je potřeba napojit výstup adderu na výstup mac
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[self.out.connect(o, self.add.out.get_wire(o), inserted_wire_desired_index=o) for o in range(0, self.out.N)]
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else:
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# Je zapotřebí zajistit ještě unikátnost jmen podkomponent a jejich vodičů pro správné generování
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mul_prefix = self.prefix + "_" + UnsignedArrayMultiplier(a=A, b=B).prefix + str(A.N)
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mul_a = Bus(prefix=f"{mul_prefix}_a", wires_list=A.bus)
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mul_b = Bus(prefix=f"{mul_prefix}_b", wires_list=B.bus)
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self.mul = self.add_component(UnsignedArrayMultiplier(a=mul_a, b=mul_b, prefix=mul_prefix))
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add_prefix = self.prefix + "_" + UnsignedRippleCarryAdder(a=R, b=self.mul.out).prefix + str(R.N)
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add_a = Bus(prefix=f"{add_prefix}_a", N=self.mul.out.N)
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add_b = Bus(prefix=f"{add_prefix}_b", wires_list=R.bus)
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# Kvůli správnému generování je potřeba správně napojit vodiče mezi mul a add
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[add_a.connect(o, self.mul.out.get_wire(o), inserted_wire_desired_index=o) for o in range(0, self.mul.out.N)]
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self.add = self.add_component(UnsignedRippleCarryAdder(a=add_a, b=add_b, prefix=add_prefix))
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# Bylo potřeba upravit definici pro výstupní sběrnici (vázanou na název top level obvodu ("ma") a mající délku jako výstup z adderu)
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self.out = Bus(self.prefix+"_out", self.add.out.N)
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# Nakonec je potřeba napojit výstup adderu na výstup mac
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[self.out.connect(o, self.add.out.get_wire(o), inserted_wire_desired_index=o) for o in range(0, self.out.N)]
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# usage
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os.makedirs("test_circuits/mac", exist_ok=True)
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mymac = MAC(Bus("a",8), Bus("b", 8), Bus("acc", 16))
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mymac.get_v_code_hier(open("test_circuits/mac/mac_hier.v", "w"))
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mymac.get_c_code_hier(open("test_circuits/mac/mac_hier.c", "w"))
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mymac.get_c_code_flat(open("test_circuits/mac/mac_flat.c", "w"))
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test = UnsignedRippleCarryAdder(Bus("a",8), Bus("b", 8))
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test.get_v_code_hier(open("test_circuits/urca_hier.v", "w"))
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@ -80,116 +80,116 @@ if __name__ == "__main__":
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# RCA
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name = f"u_rca{N}"
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circuit = UnsignedRippleCarryAdder(a, b, prefix=name)
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circuit = UnsignedRippleCarryAdder(a, b, name=name)
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export_circuit(circuit, name)
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name = f"s_rca{N}"
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circuit = SignedRippleCarryAdder(a, b, prefix=name)
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circuit = SignedRippleCarryAdder(a, b, name=name)
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export_circuit(circuit, name)
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# RCA with PG
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name = f"u_pg_rca{N}"
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circuit = UnsignedPGRippleCarryAdder(a, b, prefix=name)
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circuit = UnsignedPGRippleCarryAdder(a, b, name=name)
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export_circuit(circuit, name)
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name = f"s_pg_rca{N}"
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circuit = SignedPGRippleCarryAdder(a, b, prefix=name)
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circuit = SignedPGRippleCarryAdder(a, b, name=name)
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export_circuit(circuit, name)
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# CSKA with 4 bit CSKA blocks (default)
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name = f"u_cska{N}"
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circuit = UnsignedCarrySkipAdder(a, b, prefix=name)
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circuit = UnsignedCarrySkipAdder(a, b, name=name)
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export_circuit(circuit, name)
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name = f"s_cska{N}"
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circuit = SignedCarrySkipAdder(a, b, prefix=name)
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circuit = SignedCarrySkipAdder(a, b, name=name)
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export_circuit(circuit, name)
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# CLA with 4 bit CLA blocks (default)
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name = f"u_cla{N}"
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circuit = UnsignedCarryLookaheadAdder(a, b, prefix=name)
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circuit = UnsignedCarryLookaheadAdder(a, b, name=name)
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export_circuit(circuit, name)
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name = f"s_cla{N}"
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circuit = SignedCarryLookaheadAdder(a, b, prefix=name)
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circuit = SignedCarryLookaheadAdder(a, b, name=name)
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export_circuit(circuit, name)
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# Arrmul
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name = f"u_arrmul{N}"
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circuit = UnsignedArrayMultiplier(a, b, prefix=name)
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circuit = UnsignedArrayMultiplier(a, b, name=name)
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export_circuit(circuit, name)
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name = f"s_arrmul{N}"
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circuit = SignedArrayMultiplier(a, b, prefix=name)
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circuit = SignedArrayMultiplier(a, b, name=name)
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export_circuit(circuit, name)
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# Wallace
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name = f"u_wallace_cla{N}"
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circuit = UnsignedWallaceMultiplier(a, b, prefix=name, unsigned_adder_class_name=UnsignedCarryLookaheadAdder)
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circuit = UnsignedWallaceMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedCarryLookaheadAdder)
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export_circuit(circuit, name)
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name = f"s_wallace_cla{N}"
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circuit = SignedWallaceMultiplier(a, b, prefix=name, unsigned_adder_class_name=UnsignedCarryLookaheadAdder)
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circuit = SignedWallaceMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedCarryLookaheadAdder)
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export_circuit(circuit, name)
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name = f"u_wallace_rca{N}"
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circuit = UnsignedWallaceMultiplier(a, b, prefix=name, unsigned_adder_class_name=UnsignedRippleCarryAdder)
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circuit = UnsignedWallaceMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"s_wallace_rca{N}"
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circuit = SignedWallaceMultiplier(a, b, prefix=name, unsigned_adder_class_name=UnsignedRippleCarryAdder)
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circuit = SignedWallaceMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"u_wallace_pg_rca{N}"
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circuit = UnsignedWallaceMultiplier(a, b, prefix=name, unsigned_adder_class_name=UnsignedPGRippleCarryAdder)
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circuit = UnsignedWallaceMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedPGRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"s_wallace_pg_rca{N}"
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circuit = SignedWallaceMultiplier(a, b, prefix=name, unsigned_adder_class_name=UnsignedPGRippleCarryAdder)
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circuit = SignedWallaceMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedPGRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"u_wallace_cska{N}"
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circuit = UnsignedWallaceMultiplier(a, b, prefix=name, unsigned_adder_class_name=UnsignedCarrySkipAdder)
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circuit = UnsignedWallaceMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedCarrySkipAdder)
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export_circuit(circuit, name)
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name = f"s_wallace_cska{N}"
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circuit = SignedWallaceMultiplier(a, b, prefix=name, unsigned_adder_class_name=UnsignedCarrySkipAdder)
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circuit = SignedWallaceMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedCarrySkipAdder)
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export_circuit(circuit, name)
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# Dadda
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name = f"u_dadda_cla{N}"
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circuit = UnsignedDaddaMultiplier(a, b, prefix=name, unsigned_adder_class_name=UnsignedCarryLookaheadAdder)
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circuit = UnsignedDaddaMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedCarryLookaheadAdder)
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export_circuit(circuit, name)
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name = f"s_dadda_cla{N}"
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circuit = SignedDaddaMultiplier(a, b, prefix=name, unsigned_adder_class_name=UnsignedCarryLookaheadAdder)
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circuit = SignedDaddaMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedCarryLookaheadAdder)
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export_circuit(circuit, name)
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name = f"u_dadda_rca{N}"
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circuit = UnsignedDaddaMultiplier(a, b, prefix=name, unsigned_adder_class_name=UnsignedRippleCarryAdder)
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circuit = UnsignedDaddaMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"s_dadda_rca{N}"
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circuit = SignedDaddaMultiplier(a, b, prefix=name, unsigned_adder_class_name=UnsignedRippleCarryAdder)
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circuit = SignedDaddaMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"u_dadda_pg_rca{N}"
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circuit = UnsignedDaddaMultiplier(a, b, prefix=name, unsigned_adder_class_name=UnsignedPGRippleCarryAdder)
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circuit = UnsignedDaddaMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedPGRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"s_dadda_pg_rca{N}"
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circuit = SignedDaddaMultiplier(a, b, prefix=name, unsigned_adder_class_name=UnsignedPGRippleCarryAdder)
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circuit = SignedDaddaMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedPGRippleCarryAdder)
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export_circuit(circuit, name)
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name = f"u_dadda_cska{N}"
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circuit = UnsignedDaddaMultiplier(a, b, prefix=name, unsigned_adder_class_name=UnsignedCarrySkipAdder)
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circuit = UnsignedDaddaMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedCarrySkipAdder)
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export_circuit(circuit, name)
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name = f"s_dadda_cska{N}"
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circuit = SignedDaddaMultiplier(a, b, prefix=name, unsigned_adder_class_name=UnsignedCarrySkipAdder)
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circuit = SignedDaddaMultiplier(a, b, name=name, unsigned_adder_class_name=UnsignedCarrySkipAdder)
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export_circuit(circuit, name)
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# Arrdiv
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name = f"arrdiv{N}"
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circuit = ArrayDivider(a, b, prefix=name)
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circuit = ArrayDivider(a, b, name=name)
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export_circuit(circuit, name)
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