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5bb50a325f
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Remove iverilog from pipe
BUILD / test (push) Failing after 1m34s
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2024-11-14 15:19:54 +01:00 |
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975ab01a1c
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Fixing pipeline
BUILD / test (push) Failing after 17s
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2024-11-14 15:18:50 +01:00 |
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c476479827
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Fix mux with wrong gate ordering
BUILD / test (push) Blocked by required conditions
CodeQL / Analyze (python) (push) Failing after 39s
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2024-11-14 15:15:17 +01:00 |
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Lukas Plevac
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4eb65e10da
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All working muls and adders
BUILD / Python ${{ matrix.python-version }} test (3.11) (push) Has been cancelled
BUILD / Python ${{ matrix.python-version }} test (3.7) (push) Has been cancelled
BUILD / Python ${{ matrix.python-version }} test (3.8) (push) Has been cancelled
BUILD / Python ${{ matrix.python-version }} test (3.9) (push) Has been cancelled
BUILD / build (push) Failing after 5m29s
BUILD / test (push) Has been skipped
BUILD / Python ${{ matrix.python-version }} test (3.10) (push) Has been skipped
BUILD / documentation (push) Has been skipped
CodeQL / Analyze (python) (push) Failing after 45s
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2024-10-17 19:11:02 +02:00 |
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Lukas Plevac
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09a12f3df7
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Fully working xorGateComponent
CodeQL / Analyze (python) (push) Has been cancelled
BUILD / build (push) Has been cancelled
BUILD / test (push) Has been cancelled
BUILD / Python ${{ matrix.python-version }} test (3.10) (push) Has been cancelled
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BUILD / documentation (push) Has been cancelled
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2024-10-10 13:33:09 +02:00 |
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Lukas Plevac
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c61244c966
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Fixed RCA by test
CodeQL / Analyze (python) (push) Has been cancelled
BUILD / build (push) Has been cancelled
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BUILD / Python ${{ matrix.python-version }} test (3.10) (push) Has been cancelled
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BUILD / documentation (push) Has been cancelled
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2024-10-08 14:28:38 +02:00 |
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Lukas Plevac
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6132c3c449
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Optimalized MAJ implementation for adders
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2024-10-08 13:39:48 +02:00 |
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Lukas Plevac
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ad9f62e3de
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Added support for MIG excluded xor and xnor gate
CodeQL / Analyze (python) (push) Waiting to run
BUILD / build (push) Waiting to run
BUILD / test (push) Blocked by required conditions
BUILD / Python ${{ matrix.python-version }} test (3.10) (push) Blocked by required conditions
BUILD / Python ${{ matrix.python-version }} test (3.11) (push) Blocked by required conditions
BUILD / Python ${{ matrix.python-version }} test (3.7) (push) Blocked by required conditions
BUILD / Python ${{ matrix.python-version }} test (3.8) (push) Blocked by required conditions
BUILD / Python ${{ matrix.python-version }} test (3.9) (push) Blocked by required conditions
BUILD / documentation (push) Blocked by required conditions
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2024-10-07 15:19:55 +02:00 |
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Jan Klhůfek
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63a11f244c
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Merge pull request #27 from ehw-fit/devel
Devel
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2024-10-03 12:39:02 +02:00 |
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Vojta
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616efb25db
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workflow documentation
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2024-10-03 08:20:24 +02:00 |
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Vojta
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813f111df7
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Merge branch 'devel' of github.com:ehw-fit/ariths-gen into devel
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2024-10-03 08:19:27 +02:00 |
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Vojta
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c1e8680e83
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CGP with more than 26 inputs naming
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2024-10-03 08:18:49 +02:00 |
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Vojta Mrazek
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397876b265
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Merge pull request #26 from ehw-fit/devel
Merge Devel into Main
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2024-10-02 21:30:58 +02:00 |
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honzastor
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e804265a7b
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Updated git actions.
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2024-10-02 14:56:52 +02:00 |
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honzastor
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03212a62f5
|
Actions fix
|
2024-10-01 18:47:24 +02:00 |
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honzastor
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b87f8350fc
|
Added ripple borrow subtractor circuit and updated automated testing.
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2024-10-01 18:42:11 +02:00 |
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Vojta Mrazek
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bc95444995
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reconnected wire was not identified as a bus
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2024-07-22 15:10:21 +02:00 |
|
Vojta Mrazek
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04cd3e44d3
|
bug in cgp indexes with constant wires, they were encouted
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2024-07-22 15:09:50 +02:00 |
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Vojta Mrazek
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f34471bfe3
|
signed version of python code
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2024-07-18 13:16:15 +02:00 |
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Vojta Mrazek
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4cd1189d4a
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CGP circuit accepts BUS inputs
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2024-07-18 13:15:56 +02:00 |
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Vojta Mrazek
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bc0104de12
|
ripple cary subtractor
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2024-07-09 09:22:11 +02:00 |
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Vojta Mrazek
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e41b4a2f2c
|
Merge branch 'devel' of github.com:ehw-fit/ariths-gen into devel
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2024-07-08 11:31:30 +02:00 |
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Vojta Mrazek
|
c480eeacf9
|
popcount parent component
|
2024-07-08 11:29:25 +02:00 |
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honzastor
|
ce36ebf77b
|
Fixed hierarchical BLIF generation for popcount_compare.
|
2024-04-17 18:47:41 +02:00 |
|
honzastor
|
f4b816fc09
|
Fix for workflow tests
|
2024-04-14 16:36:45 +02:00 |
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honzastor
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6003886eb7
|
Fixed hierarchical Verilog generation of popcount compare. BLIF probably needs a similar treatment, TBD later
|
2024-04-14 16:29:10 +02:00 |
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honzastor
|
97e79b93da
|
Big code cleanup and some fixes. Hierarchical generation for popcount seems problematic. It seems bus connections are the issue.
|
2024-04-13 17:04:03 +02:00 |
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honzastor
|
739d5fafce
|
Added documentation to Recursive multiplier and hopefully fixed some issues with popcount output generation.
|
2024-04-08 21:37:34 +02:00 |
|
Vojta Mrazek
|
4e331f0525
|
popcount with variable sizes
|
2024-04-08 13:48:25 +02:00 |
|
Jan Klhůfek
|
211dd49fb5
|
Merge pull request #25 from ehw-fit/popcount
Popcount
|
2024-04-05 12:40:39 +02:00 |
|
Vojta Mrazek
|
0180735dd5
|
workflow to node.js 20
|
2024-04-05 11:27:41 +02:00 |
|
Vojta Mrazek
|
84a41ad93c
|
test unique #21
|
2024-04-05 11:25:37 +02:00 |
|
Vojta Mrazek
|
77724ad115
|
workflow update
|
2024-04-05 11:21:42 +02:00 |
|
Vojta Mrazek
|
128b1309a1
|
popcount fixes
|
2024-04-05 09:24:03 +02:00 |
|
Vojta Mrazek
|
8468c5b8fd
|
Merge pull request #24 from ehw-fit/devel
Devel merge to popcount
|
2024-04-05 09:19:26 +02:00 |
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Vojta Mrazek
|
1219d7bec5
|
Merge branch 'popcount' into devel
|
2024-04-05 09:19:04 +02:00 |
|
Vojta Mrazek
|
2cf7b921ea
|
Popcount implementation
|
2024-04-05 08:46:02 +02:00 |
|
honzastor
|
da733cf44e
|
Added instantiation of wires and buses from inputs. Hopefully fixed now.
|
2024-03-28 00:06:53 +01:00 |
|
honzastor
|
cd3441ff00
|
Removed error tests from overall testing.
|
2024-03-27 23:44:34 +01:00 |
|
honzastor
|
21a6437eb8
|
Additional type hint fix.
|
2024-03-27 23:19:40 +01:00 |
|
honzastor
|
73101eb055
|
Type hint bugfix for pytest.
|
2024-03-27 23:10:06 +01:00 |
|
honzastor
|
d013a40145
|
Added unsigned recursive multiplier and made some bugfixes.
|
2024-03-27 23:00:13 +01:00 |
|
Vojta Mrazek
|
2e1694ccd5
|
popcount and compare
|
2024-03-22 14:19:23 +01:00 |
|
honzastor
|
7e1112cf81
|
Added individual input bus attributes to CGP Circuit objects to allow for the generation of output CGP representation.
|
2024-03-06 00:42:12 +01:00 |
|
Vojta Mrazek
|
f853a46703
|
CGP circuit checks
|
2023-04-13 12:09:07 +02:00 |
|
Vojta Mrazek
|
a44b0638a1
|
Implementation of QuAd approximate adder
|
2023-03-28 13:55:58 +02:00 |
|
Vojta Mrazek
|
a4741db191
|
connection checks (asserts)
|
2023-03-28 11:16:55 +02:00 |
|
Vojta Mrazek
|
44e0a920d1
|
MUX support of constant values
|
2023-03-24 12:11:42 +01:00 |
|
Vojta Mrazek
|
49bbc86a0f
|
accepts a wire as a bus
|
2023-03-23 13:39:32 +01:00 |
|
Vojta Mrazek
|
363e402e16
|
workflow: docs
|
2023-03-23 08:00:37 +01:00 |
|
