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Author	SHA1	Message	Date
Jan Klhůfek	f6838e50bd	Merge pull request #4 from honzastor/develop ... Merging current final state of ArithsGen into main branch.	2021-04-24 00:04:31 +02:00
honzastor	4740371c06	Deleted presentation of previous generator state.	2021-04-24 00:00:48 +02:00
honzastor	0f66c5a2e9	Fixed proper connections in submodules instantiation in hierarchical Verilog generation. Sample generated circuits were also accordingly updated.	2021-04-23 11:49:24 +02:00
honzastor	a17e38b2d1	Uploading C code circuit simulations.	2021-04-23 02:48:32 +02:00
honzastor	670ba45ee5	Generated sample circuits for various representations. Updated C code circuits testing simulations and did some cleanup.	2021-04-23 02:44:14 +02:00
honzastor	f57a633f6c	Renamed generated circuits folders.	2021-04-22 20:56:38 +02:00
honzastor	8f911560b0	Folder renaming test	2021-04-22 20:23:57 +02:00
honzastor	ad1c6ec557	Updated circuits documentation.	2021-04-21 13:42:07 +02:00
honzastor	8e950fc51f	Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits.	2021-04-21 11:33:07 +02:00
honzastor	068def0226	Added documentation of classes methods.	2021-04-06 01:39:11 +02:00
honzastor	a328e91996	Removed automatic documentation generation from git action.	2021-03-31 04:43:35 +02:00
honzastor	a336a683e7	Added some code documentation and updated git action to generate it.	2021-03-31 04:40:54 +02:00
honzastor	7a6d5213f8	Updating gitignore	2021-03-30 16:15:54 +02:00
honzastor	8807ebfb66	Merge branch 'develop' of https://github.com/honzastor/bc_arithmetic_circuits_generator into develop	2021-03-30 16:14:45 +02:00
honzastor	5fe150a824	Adding possibility for automatic generation using git actions.	2021-03-30 16:13:42 +02:00
Jan Klhůfek	82d2d02ef5	Delete ariths_gen/one_bit_circuits/logic_gates/__pycache__ directory	2021-03-30 03:13:15 +02:00
Jan Klhůfek	debef13087	Delete ariths_gen/one_bit_circuits/one_bit_components/__pycache__ directory	2021-03-30 03:13:04 +02:00
Jan Klhůfek	9a4c2c4dd7	Delete ariths_gen/multi_bit_circuits/multipliers/__pycache__ directory	2021-03-30 03:12:43 +02:00
Jan Klhůfek	d27fbf7088	Delete ariths_gen/multi_bit_circuits/adders/__pycache__ directory	2021-03-30 03:12:31 +02:00
Jan Klhůfek	669920b0d5	Delete ariths_gen/wire_components/__pycache__ directory	2021-03-30 03:12:11 +02:00
Jan Klhůfek	1e2ae53df5	Delete ariths_gen/one_bit_circuits/__pycache__ directory	2021-03-30 03:11:57 +02:00
Jan Klhůfek	e28574a7c9	Delete ariths_gen/multi_bit_circuits/__pycache__ directory	2021-03-30 03:11:38 +02:00
Jan Klhůfek	87105eaaa6	Delete ariths_gen/core/__pycache__ directory	2021-03-30 03:11:13 +02:00
Jan Klhůfek	86479086c0	Delete ariths_gen/__pycache__ directory	2021-03-30 03:11:03 +02:00
honzastor	4a9408401e	Typo fix.	2021-03-30 03:06:41 +02:00
honzastor	69e2514852	Updated project's structure. Renamed class names to properly fit Python naming convention. TBD: proper documentation.	2021-03-30 03:04:48 +02:00
honzastor	27866a5513	Made some bugfixes concerning hierarchical generation and updated generated circuits.	2021-03-29 22:50:24 +02:00
honzastor	f7620f98e4	Generated various circuits representations and updated testing of C circuits.	2021-03-28 20:16:45 +02:00
honzastor	acd3d51a62	Updating some minor changes.	2021-03-28 18:17:10 +02:00
Jan Klhůfek	6f02fa94d1	Deleting docs folder for GIT consistency	2021-03-23 16:13:51 +01:00
Vojta Mrazek	af8cd2c93b	no actions	2021-03-23 14:05:54 +01:00
Vojta Mrazek	ec09e606b9	Merge branch 'develop' of github.com:honzastor/bc_arithmetic_circuits_generator into develop	2021-03-23 14:04:57 +01:00
github-actions[bot]	07a16a498c	[create-pull-request] automated change	2021-03-23 14:04:18 +01:00
Vojta Mrazek	9e99c98220	Merge pull request #2 from honzastor/create-pull-request/patch ... Changes by create-pull-request action	2021-03-23 13:51:57 +01:00
github-actions[bot]	7ba6db3e54	[create-pull-request] automated change	2021-03-23 12:50:43 +00:00
Vojta Mrazek	ac2654b527	Merge pull request #1 from mrazekv/develop ... Develop	2021-03-23 13:49:37 +01:00
Vojta Mrazek	a8a8779616	action2	2021-03-23 13:46:23 +01:00
Vojta Mrazek	915f494331	workflow	2021-03-23 13:41:56 +01:00
honzastor	5788b6a879	Pushing circuits generation example.	2021-03-22 10:49:54 +01:00
honzastor	8df8e72810	Test commit	2021-03-22 00:31:59 +01:00
honzastor	792d0c5db1	Did some code refactoring concerning one bit circuits generation. Added multiple one/multi bit circuits. TBD: Generate and test different circuits, implement divider circuits, comment code, add verification/optimization of Verilog/BLIF files using yosys tool.	2021-03-22 00:22:01 +01:00
honzastor	d86ddcac09	Implemented unsigned dadda multiplier circuit. Updated generation of export formats. TBD: Proper testing, modification of dadda with cla adder, write shell script for Verilog and Blif equivalence check.	2021-03-15 01:08:47 +01:00
honzastor	f76284fcaa	Updated cgp chromosomes for 1 bit multipliers.	2021-03-04 19:34:08 +01:00
honzastor	e8cffeca91	Generated and tested generated circuits.	2021-03-04 18:59:33 +01:00
honzastor	f28069da5f	Refactored code and made some small bugfixes for generating exports.	2021-03-04 18:57:32 +01:00
honzastor	3aa6ecc368	Merge branch 'develop' of https://github.com/honzastor/bc_arithmetic_circuits_generator into develop	2021-03-01 21:41:37 +01:00
honzastor	7a37a646c6	Pushing last updated file.	2021-03-01 21:38:04 +01:00
Jan Klhůfek	2e80db21bc	Delete logic_gates_generator.py ... Outdated file, replaced by logic_gates.py	2021-03-01 21:36:23 +01:00
honzastor	e4722c662d	Implemented multiplier circuits, verilog and cgp export generation and changed generator's structure. Prone to error! Needs proper testing. TBD	2021-03-01 21:32:29 +01:00
honzastor	ef5dc80382	Implemented generation to flat Verilog format and improved some other minor bits of code.	2021-02-16 10:41:29 +01:00